Simplified differential signaling

• US 6,628,721 B1
• Filed: 11/24/1999
• Issued: 09/30/2003
• Est. Priority Date: 11/24/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Fischer, Jonathan Herman
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): TRAN, KHANH C
• Application Number:
  US09/448,934
• Time in Patent Office: 1,406 Days
• Field of Search: 375/259, 375/257, 375/220, 375/219, 375/222, 375/295, 375/296, 327/107, 327/108, 327/110, 327/52, 327/53, 327/56, 327/65, 327/68, 327/72, 327/77, 327/89, 327/404, 327/407, 327/408, 326/20, 326/21, 326/26, 326/27, 326/30, 326/83, 326/119, 326/121, 326/34
• US Class Current: 375/257
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

A method and apparatus for transmitting and receiving digital data in a noisy environment. Digital data is transmitted with a degree of noise immunity by generating and transmitting a reference signal along with the transmitted digital data signal. The reference signal has a voltage level between a logic level low and a logic level high of the digital data signal. The reference signal can be used to identify the center point of the transmitting device logic levels. Furthermore, the reference signal allows the receiver to track and compensate for noise introduced at the transmitter of the digital data signal.

Claims

1. In the manufacture of an electronic component from an integrated circuit and a package having parasitic inductance, the integrated circuit comprising:

a transmitter for transmitting a digital data signal, and

a reference circuit for generating and transmitting a reference signal, the reference signal being at a voltage between a logic level low and a logic level high of the digital data signal, wherein the reference circuit includes a pair of resistive elements placed in series between a power source and a return for the power source, such that the reference signal is generated at the connection between the pair of resistive elements.

2. The integrated circuit according to claim 1, wherein the reference circuit generates a reference signal that varies such that the reference signal voltage remains approximately midway between a variable logic level low and a variable logic level high.

3. The integrated circuit according to claim 1, wherein the pair of resistive elements have approximately equal resistance.

4. The integrated circuit according to claim 1, wherein the reference circuit generates a reference signal having a voltage that is approximately midway between the logic level low and the logic level high.

5. The integrated circuit according to claim 1, wherein the reference circuit generates a reference signal having a voltage level dependent upon the level of parasitic inductance in the electronic component.

6. A receiver for receiving a digital signal, comprising:

a switch circuit for generating a switching point signal as a function of an input reference signal, the switching point signal identifying the transition between a logic level low and a logic level high in the received digital signal,

a comparator for comparing the received digital signal with the switching point signal in order to determine whether the received digital signal is a logic level low or a logic level high; and

a routing switch operably coupled between the switch circuit and the comparator,the routing switch receiving the low level switching signal and the high level switching signal as inputs from the switch circuit, and the routing switch generating a processed switching signal as an output to the comparator.

7. The receiver according to claim 6, further comprising an input line for receiving the reference signal.

8. The receiver according to claim 6, wherein the switch circuit includes a voltage step down circuit for generating a low level switching signal as a function of the input reference signal, the low level switching signal being at a voltage level less than the input reference signal.

9. The receiver according to claim 8, wherein the voltage step down circuit further comprises a resistor in series with a supplemental power source, wherein the combination of the resistor and the supplemental power source is operably coupled between the input reference signal and a ground signal.

10. The receiver according to claim 6, wherein the switch circuit includes a voltage step up circuit for generating a high level switching signal as a function of the input reference signal, the high level switching signal being at a voltage greater than the input reference signal.

11. The receiver according to claim 10, wherein the voltage step up circuit further comprises a resistor in series with a supplemental power source, wherein the combination of the resistor and the supplemental power source is operably coupled between the input reference signal and a primary power signal.

12. The receiver according to claim 6, wherein switch circuit includes circuitry for generating a high level switching signal and a low level switching signal as a function of the input reference signal.

13. A receiver for receiving a digital signal, comprising:

a switch circuit for generating a switching point signal as a function of an input reference signal, the switching point signal identifying the transition between a logic level low and a logic level high in the received digital signal,

a comparator for comparing the received digital signal with the switching point signal in order to determine whether the received digital signal is a logic level low or a logic level high; and

a routing switch operably coupled between the switch circuit and the comparator, the routing switch receiving the low level switching signal and the high level switching signal as inputs from the switch circuit, and the routing switch generating a processed switching signal as an output to the comparator, wherein the routing switch outputs either the low level switching signal or the high level switching signal to the comparator as a function of the output of the comparator.