Method and apparatus for manipulating vectored data

• US 6,629,115 B1
• Filed: 10/01/1999
• Issued: 09/30/2003
• Est. Priority Date: 10/01/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Rossignol, Stephane
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US09/411,789
• Time in Patent Office: 1,460 Days
• Field of Search: 708/209, 377/64, 377/67, 377/68, 377/69, 377/70, 712/300
• US Class Current: 708/209
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 5/015 having at least two separately controlled shifting levels, e.g. using shifting matrices G06F5/012 takes precedence
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value

Abstract

A method and apparatus is disclosed for manipulating vectored data. The method includes shifting bits of packed data comprising M N-bit elements using a bit-level shift step followed by a byte-level shift step. A mask is generated and applied to the intermediate shifted result to produce the final result. A method is disclosed for conditionally transferring data from one general purpose register to another based on data in yet a third general purpose register.

Claims

1. In a RISC-based computer processing core having a general purpose register file, a method of shifting packed data of M N-bit elements comprising steps of:

receiving an instruction, the instruction specifying a shift amount and a shift direction; and

decoding the instruction to produce control signals;

in response to the control signals;

selecting one of the general purpose registers;

bit-level shifting the data contained therein by a first amount based on the shift amount and by at most seven bit positions to produce a bit-shifted datum;

re-ordering the bits of the bit-shifted datum to produce an intermediate result representative of a byte-level shifting of the bit-shifted datum by a second amount based on the shift amount;

producing a mask based on the shift amount; and

for each bit in the intermediate result, either producing the bit or producing a preselected bit value based on the mask to form a final result.

2. The method of claim 1 wherein the preselected bit value is logic ‘

0’

.

3. The method of claim 1 further including feeding each bit of the intermediate result into one input of a 2:

1 selector, the other inputs of the selectors receiving a logic ‘

0’

;

feeding each bit of the mask into a select control input of each of the selectors.

4. The method of claim 1 wherein the first amount is the shift amount modulo 8.

5. The method of claim 4 further including reading out a sign bit from each of said data and wherein the preselected value is either a logic ‘

0’

or a logic ‘

1’

based on the sign bits.

6. The method of claim 4 further including feeding each bit of the intermediate result into one input of a 2:

1 selector, the other inputs of the selectors receiving a logic value based on the sign bits;

feeding each bit of the mask into a select control input of each of the selectors.

7. The processing core of claim 1 wherein M is 4 and N is 16.

8. The processing core of claim 1 wherein M is 2 and N is 32.

9. A processing core having circuitry for shifting bits of packed N-bit data by a shift amount, the circuitry comprising:

an input for providing a packed N-bit datum, comprising M N-bit elements;

shift circuitry having an input to receive the packed datum and effective for shifting the M×

N bits of the packed datum by the shift amount to produce a shifted output, the shift circuitry comprising a bit shifter for shifting the packed datum by an amount up to seven bit positions to produce a first result and a matrix operable to re-order at least some of the bits in the first result in any order to produce the shifted output;

mask generation logic to produce a mask, the bit-pattern of the mask based on the value of N and the shift amount;

an alternate logic value generator for producing M×

N bit values; and

selector logic effective for producing, for each bit in the shifted output, either that bit or one of the M×

N bit values based the mask bits.

10. The processing core of claim 9 wherein the bit-pattern of the mask comprises M groups of N bits each, each group having a contiguous run of ones and a contiguous run of zeroes, either the run of ones or the run of zeroes being equal to the shift amount.

11. The processing core of claim 9 wherein the selector logic includes a plurality of 2:

1 selectors, each having a first input coupled to receive one of the bits in the shifted output and a second input coupled to receive one of the M×

N bit values, each selector having an select input coupled to one of the mask bits.

12. The processing core of claim 9 wherein the shift circuitry includes a bit shift unit having and input effective for receiving a packed N-bit datum, and a byte shift unit coupled to receive the output of the bit shift unit.

13. The processing core of claim 9 further including a data path from the sign-bit position of each of the M N-bit data coupled to the alternate logic value generator, the M×

N bit values being based on the sign-bits.

14. The processing core of claim 13 wherein the M×

N bit values comprises a pattern of M N-bit groups, each group having a contiguous run of a first logic value equal to the shift amount and a contiguous run of a second logic value equal to the difference between N and the shift amount, the second logic value being based on one of the sign bits.

15. The processing core of claim 9 wherein M is 4 and N is 16.

16. The processing core of claim 9 wherein M is 2 and N is 32.

17. A processing core comprising:

bit shifting logic in data communication with the register file, the register file effective for providing the contents of two or three registers;

byte shifting logic in data communication with a first output of the bit shifting logic;

a plurality of 2;

1 selectors, each having a first input coupled to an output of the byte shifting logic;

a sign generator in data communication with a second output of the bit shifting logic, the sign generator having an output coupled to a second input of the selector; and

a mask generator having outputs coupled to the select inputs of the selectors,

the byte-shifting logic configured to receive the first output and to output at least some of the bits comprising the first output in any order, to produce the output of the byte-shifting logic.

18. The processing core of claim 17 wherein the bit shifting logic, byte shifting logic, sign generator, and the mask generator are responsive to the decoding of a shift instruction.

19. The processing core of claim 18 wherein the shift instruction is one of MMSHLLD.W, MMSHLRD.W, MMSHLLD.L, MMSHLRD.L, MSHARD.W, and MSHARD.L,

wherein MMSHLLD.W is a logical left shift of a packed 16-bit datum,

wherein MMSHLRD.W is a logical right shift of a packed 16-bit datum,

wherein MMSHLLD.L is a logical left shift of a packed 32-bit datum,

wherein MMSHLRD.W is a logical right shift of a packed 16-bit datum

wherein MMSHARD.W is an arithmetic right shift of a packed 16-bit datum, and

wherein MMSHARD.L is an arithmetic right shift of a packed 16-bit datum.

20. The processing core of claim 18 wherein the byte shifting logic is further responsive to the decoding of one of the MCNVS.WB, MCNVS.WUB, and MCNVS.LW instructions,

wherein MCNVS.WB is a conversion of signed 16-bit data to signed 8-bit values,

wherein MCNVS.WUB is a conversion of signed 16-bit data to unsigned 8-bit values, and

wherein MCNVS.LW is a conversion of 32-bit data to signed 16-bit values.

21. The processing core of claim 20 wherein the byte shifting logic is further responsive to the decoding of one of the MSHFHI.B, MSHFLO.B, MSHFHI.W, MSHFLO.W, MSHFHI.L, MSHFLO.L instructions,

wherein MSHFHI.B is an interleave of 8-bit data stored in an upper portion of a first operand associated with the instruction with 8-bit data stored in an upper portion of a second operand associated with the instruction,

wherein MSHFLO.B is an interleave of 8-bit data stored in a lower portion of a first operand associated with the instruction with 8-bit data stored in a lower portion of a second operand associated with the instruction,

wherein MSHFHI.W is an interleave of 16-bit data stored in an upper portion of a first operand associated with the instruction with 16-bit data stored in an upper portion of a second operand associated with the instruction,

wherein MSHFLO.W is an interleave of 16-bit data stored in a lower portion of a first operand associated with the instruction with 16-bit data stored in a lower portion of a second operand associated with the instruction,

wherein MSHFHI.L is an interleave of 32-bit data stored in an upper portion of a first operand associated with the instruction with 32-bit data stored in an upper portion of a second operand associated with the instruction, and

wherein MSHFLO.L is an interleave of 32-bit data stored in a lower portion of a first operand associated with the instruction with 32-bit data stored in a lower portion of a second operand associated with the instruction.

22. The processing core of claim 21 wherein the byte shifting logic is further responsive to the decoding of an MPERM.W instruction,

wherein MPERM.W permutes an ordering of 16-bit data stored in a first operand associated with the instruction according to data stored in a second operand associated with the instruction.

23. The processing core of claim 22 wherein the byte shifting logic is further responsive to the decoding of one of the MEXTR1, MEXTR2, MEXTR3, MEXTR4, MEXTR5, MEXTR6, and MEXTR7 instructions,

wherein MEXTRn extracts eight bytes of data from two concatenated operands associated with the instruction, the eight bytes being offset from the right side of the concatenated operands by “

n”

bytes.