Solving parallel problems employing hardware multi-threading in a parallel processing environment

• US 6,629,237 B2
• Filed: 01/12/2001
• Issued: 09/30/2003
• Est. Priority Date: 09/01/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wheeler, William R., Wolrich, Gilbert, Adiletta, Matthew J.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US09/759,380
• Publication Number:
  US 20020053016A1
• Time in Patent Office: 991 Days
• Field of Search: 712/1, 712/34, 712/228, 712/246
• US Class Current: 712/228
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A computer instruction includes a command instruction to issue a memory reference to an address in a memory shared among threads executing in microprocessors while a context of a thread is inactive.

Claims

1. An execution unit for executing multiple context threads comprises:

an arithmetic logic unit to process data for executing threads;

control logic to control the operation of the arithmetic logic unit;

context event switching logic including signal inputs from a plurality of shared resources with the signal inputs causing the context event logic to indicate that threads are either available or unavailable for execution;

a set of memory location for storing a list of available threads that are ready to be executed;

a set of memory locations for storing a list of unavailable threads that are not ready to be executed;

general purpose register set to store and obtain operands for the arithmetic logic unit;

a read transfer register for inputting data to the execution unit, the read transfer register accessible to at least one of the plurality of shared resources;

a write transfer register for outputting data from the execution unit, the write transfer register accessible to at least one of the plurality of shared resources;

wherein the read and write transfer register sets are divided into a plurality of banks and a plurality of relatively addressable windows that correspond to individual threads to execute in the processor and where execution of a read or write instruction to a memory location causes a corresponding read or write to a location in the transfer registers.

2. The execution unit of claim 1 wherein the read or write instruction specifies an optional token.

3. The execution unit of claim 2 wherein the optional token specifies ctx_swap and causes the currently running thread to be swapped out to the unavailable thread memory set and a thread from the available thread memory set to begin execution.

4. The execution unit of claim 2 wherein the optional token specifies defer_one and causes execution of one more instruction and then causes the current context to be swapped out.

5. The execution unit of claim 2 wherein the read instruction optional token specifies one of the signal inputs and causes a currently running thread to be swapped out to the unavailable thread memory set, and upon receipt of the specified signal input causes the swapped out thread to be stored in the available thread memory set and indicates the requested data is available in the transfer register.

6. The execution unit of claim 2 wherein the write instruction optional token specifies one of the signal inputs and causes a currently running thread to be swapped out to the unavailable thread memory set and upon receipt of the specified signal input causes the swapped out thread to be stored in the available thread memory set and indicates the specified data has been sent out to memory.

7. A processor unit comprises:

an execution unit for executing multiple context threads comprising;

an arithmetic logic unit to process data for executing threads;

control logic to control the operation of the arithmetic logic unit;

context event switching logic including signal inputs from a plurality of shared resources with the signal inputs causing the context event logic to indicate that threads are either available or unavailable for execution;

a set of memory locations for storing a list of available threads that are ready to be executed;

a set of memory locations for storing a list of unavailable threads that are not ready to be executed;

general purpose register set to store and obtain operands for the arithmetic logic unit;

a read transfer register for inputting data to the execution unit, the read transfer register accessible to at least one of the plurality of shared resources; and

a write transfer register for outputting data from the execution unit, the write transfer register accessible to at least one of the plurality of shared resources.

8. The processor of claim 7 wherein the read and write transfer register sets are divided into a plurality of banks and a plurality of relatively addressable windows that correspond to individual threads to execute in the processor and where execution of a read or write instruction to a memory location causes a corresponding read or write to a location in the transfer registers.

9. The processor of claim 8 wherein the read or write instruction specifies an optional token.

10. The processor of claim 9 wherein the optional token specifies ctx_swap and causes the currently running thread to be swapped out to the unavailable thread memory set and a thread from the available thread memory set to begin execution.

11. The processor of claim 9 wherein the optional token specifies defer_one and causes execution of one more instruction and then causes the current context to be swapped out.

12. The processor of claim 9 wherein the read instruction optional token specifies one of the signal inputs and causes a currently running thread to be swapped out to the unavailable thread memory set, and upon receipt of the specified signal input causes the swapped out thread to be stored in the available thread memory set and indicates the requested data is available in the transfer register.

13. The processor of claim 9 wherein the write instruction optional token specifies one of the signal inputs and causes a currently running thread to be swapped out to the unavailable thread memory set and upon receipt of the specified signal input causes the swapped out thread to be stored in the available thread memory set and indicates the specified data has been sent out to memory.

14. A method for executing multiple context threads comprises:

processing data for executing thread within an arithmetic logic;

operating control logic to control the arithmetic logic;

operating context event switching logic with the context event logic constructed with signal inputs from a plurality of shared resources and with the signal inputs causing the context event logic to indicate that threads are either available or unavailable for execution;

storing and obtaining operands for the arithmetic logic unit within a general purpose register set;

inputting data from memory through a read transfer register;

outputting data to memory through a write transfer register;

accessing data from at least one of the read transfer register and the write transfer register by at least one of the plurality of shared resources; and

arranging the read and write transfer register sets into a plurality of banks and a plurality of relatively addressable windows that correspond to individual threads which may be executed in the processor.

15. The method of claim 14 wherein reading or writing to memory causes a corresponding reading or writing to a location in the transfer registers.

16. The method of claim 15 wherein reading or writing to memory includes specifying an optional token.

17. The method of claim 16 wherein specifying the optional token as ctx_swap causes the currently running thread to be swapped out.

18. The method of claim 15 wherein specifying the optional token as one of the signal inputs causes the context event logic to swap out the currently executing thread and upon receipt of the specified signal input causes the context event logic to indicate that the swapped out thread is available for execution.

19. An article comprising a machine-readable medium having stored thereon machine-executable instructions that when executed by a machine causes the machine to:

process data for executing thread within an arithmetic logic;

operate control logic to control the arithmetic logic;

operate context event switching logic with the context event logic constructed with signal inputs from a plurality of shared resources and with the signal inputs causing the context event logic to indicate that threads are either available or unavailable for execution;

store and obtain operands for the arithmetic logic unit within a general purpose register set;

input data from memory through a read transfer register;

output data to memory through a write transfer register;

access data from at least one of the read transfer register and the write transfer register by at least one of the plurality of shared resources; and

arrange the read and write transfer register sets into a plurality of banks and a plurality of relatively addressable windows that correspond to individual threads which may be executed in the processor.

20. The article of claim 19 further comprising a machine-readable medium having stored thereon machine-executable instructions that when executed by a machine causes the machine to:

read or write to memory and cause a corresponding read or write to a location in the transfer registers.

21. The article of claim 20 further comprising a machine-readable medium having stored thereon machine-executable instructions that when executed by a machine causes the machine to:

specify an optional token when reading or writing to memory.

22. The article of claim 21 further comprising a machine-readable medium having stored thereon machine-executable instructions that when executed by a machine causes the machine to:

specify the optional token as ctx swap; and

swap out the currently running thread.

23. The article of claim 20 further comprising a machine-readable medium having stored thereon machine-executable instructions that when executed by a machine causes the machine to:

specify the optional token as one of the signal inputs; and

swap out the currently executing thread; and

upon receipt of the specified signal input indicate that the swapped out thread is available for execution.