Functional verification of integrated circuit designs

• US 6,629,296 B1
• Filed: 07/28/2000
• Issued: 09/30/2003
• Est. Priority Date: 06/16/1997
• Status: Expired due to Term

• Current Assignee: Synopsys Emulation and Verification SA (Synopsys Incorporated)
• Original Assignee: Tharas Systems, Inc. (Synopsys Incorporated)
• Inventors: Pillalamarri, Shyam Prasad, Ganesan, Subbu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/627,347
• Time in Patent Office: 1,159 Days
• Field of Search: 716/5, 716/4, 716/8
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding to the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Claims

1. A combinatorial logic output evaluator (CLOE) for use in a functional verification system, said functional verification system being used in the functional verification of a target design partitioned into a plurality of combinatorial blocks, each of said combinatorial blocks having an associated truth table, wherein each of said truth tables represents an output value corresponding to each combination of input values of the corresponding combinatorial block, said CLOE comprising:

a plurality of random access storage devices (RASDs), each RASD containing a plurality of memory locations accessible by a corresponding memory address, wherein the output value of each row of said plurality of truth tables is stored at a memory location having a memory address formed by the input values for the row such that each of said plurality of combinatorial blocks can be evaluated by accessing said RASD having a memory address formed by the input values for the truth table, wherein each of said plurality of RASDs comprises at least 1000 memory locations; and

a plurality of cross-connects (XCONs), each of said XCONs being coupled to one or more of said RASDs, said plurality of XCONs evaluating each of said plurality of combinatorial blocks for an input combination by sending said input combination as said memory address to the corresponding RASD.

2. The CLOE of claim 1, wherein said plurality of RASDs and said plurality of XCONs are implemented in a plurality of chassis, with each chassis including a plurality of boards, with each board including a plurality of XCONs.

3. The CLOE of claim 2, wherein said plurality of XCONs in a board include a central XCON for providing intra-board communication with XCONs in another boards, wherein communication between CLOEs enables said system to maintain dependencies in said target design.

4. The CLOE of claim 1, wherein each of said plurality of XCONs forms a location address of a RASD from the input values corresponding to combinatorial blocks stored in the RASD.

5. The CLOE of claim 4, wherein each of said plurality of XCONs comprises a local storage for storing the output values retrieved from said plurality of RASDs such that said stored output values can be provided as a part of said location address during a subsequent machine cycle.

6. The CLOE of claim 5, wherein each of said plurality of XCONs further comprises a second multiplexor coupled to the output of said first multiplexor, said second multiplexor receiving an access unit from one of said plurality of RASDs, said access unit comprising a plurality of output values, said second multiplexor receiving a control word from said first multiplexor, said control word causing said second multiplexor to select one of said plurality of output values in said access unit, said selected output value corresponding to a desired output value.

7. The CLOE of claim 5, wherein each of said plurality of XCONs further comprises:

a first bus coupled to XCONs on an external board, wherein said bus is designed to receive and send output values between XCONs located on different boards;

a third multiplexor for receiving the output values stored in said local storage and selectively providing said output values on said bus; and

a tri-state buffer coupled between said third multiplexor and said bus, said tri-state buffer enabling said third multiplexor to send output values on said bus, and isolating said third multiplexor from said bus when output values are received on said third multiplexor.

8. The CLOE of claim 7, wherein each of said plurality of XCONs further comprises a fourth multiplexor coupled to a plurality of XCONs located on a single board, said fourth multiplexor selectively forwarding as an output one of a bit received on said first bus, a bit received on a third bus coupled to an XCON on said single board, a bit from said local storage, and a bit received from one of said plurality of RASDs in the same machine cycle.

9. The CLOE of claim 1, wherein each of said plurality of XCONs further comprises a first multiplexor for selecting as a bit of said location address one of said stored output value bit, a bit from a neighboring XCON, a bit from a different chassis, and a bit of a primary input.

10. The CLOE of claim 9, wherein each of said plurality of XCONs further comprises a first multiplexor controller for controlling the sequence of selections of said multiplexor, wherein said first multiplexor controller is configured according to the division of said target design such that the data dependencies in said target design are preserved during the evaluation of said plurality of combinatorial blocks.

11. The CLOE of claim 10, wherein each of said plurality of XCONs further comprises counter coupled to said first multiplexor, said counter being configured to provide a bit of said location address when the aggregate number of input bits of blocks stored in a RASD is less than the number of bits in said location address.

12. The CLOE of claim 11, wherein said first multiplexor controller comprises a stack.

13. The CLOE of claim 1, wherein said CLOEs are coupled to an external system, wherein said target design represents a component of said external system, said CLOE receiving as said plurality of primary outputs the input data values which said component would have received, and providing said plurality of primary outputs as outputs of said component such that said system can be used in an emulation environment.