Tracing the change of state of a signal in a functional verification system

• US 6,629,297 B2
• Filed: 12/14/2000
• Issued: 09/30/2003
• Est. Priority Date: 12/14/2000
• Status: Expired due to Term

• Current Assignee: Synopsys Emulation and Verification SA (Synopsys Incorporated)
• Original Assignee: Tharas Systems, Inc. (Synopsys Incorporated)
• Inventors: Broukhis, Leonid Alexander, Narayanaswamy, Ramesh, Nixon, Ian Michael, Ganesan, Subbu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/738,259
• Publication Number:
  US 20020116693A1
• Time in Patent Office: 1,020 Days
• Field of Search: 716/5, 716/4, 716/7
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

Claims

1. A tracing circuit to trace the change of state of a plurality of signals, wherein each of said signals represents the output resulting from the evaluation of a combinatorial block and/or a plurality of state elements, said combinatorial blocks and/or a plurality of state elements together forming a target design of a functional verification system, the present value of a cluster of said signals being received in pre-specified bit positions of a bus, said bus being shared by a plurality of clusters including said cluster to send corresponding signals, said tracing circuit comprising:

a mask memory containing a plurality of mask locations, each mask location indicating the bit positions of said bus on which the present value of each of a corresponding cluster of signals is to be received;

a previous state memory storing a previous value for each of said plurality of signals;

a trace buffer; and

a trace controller coupled to said mask memory, said previous state memory and said trace buffer, said trace controller receiving a cluster identifier and a plurality of bits, said cluster identifier identifying the corresponding cluster to which said plurality of bits relate to, said plurality of bits being received on said bus and representing present values for the signals in the cluster identified by said cluster identifier at bit positions indicated by the corresponding mask location,

said trace controller comparing said plurality of bits with corresponding previous values to determine if there is a change in any of the signal values in said cluster identified by said cluster identifier, said trace controller storing an entry in said trace buffer indicating that change has occurred if a change is detected based on the comparison.

2. The tracing circuit of claim 1, wherein each of said mask memory and said previous state memory comprise a number of locations equal to the number of clusters such that said trace controller can access said mask memory and said previous state memory using said cluster identifier.

3. The tracing circuit of claim 1, wherein said trace controller stores said plurality of bits into said previous state memory to reflect the change in values of corresponding signals if a change is detected.

4. The tracing circuit of claim 1, wherein said trace controller is designed to receive a push timer signal, said trace controller storing an entry in said trace buffer responsive to the assertion of said push timer signal, wherein said entry enables the status of different signals to be examined at the time of assertion of said push timer signal.

5. The tracing circuit of claim 1, wherein said trace buffer is implemented as a plurality of banks such that said trace controller can write into at least one of the banks while the trace results can be retrieved from another bank in parallel.

6. The tracing circuit of claim 5, wherein each of said banks is implemented as a random access memory (RAM), with each RAM location storing said cluster number and said plurality of bits.

7. The tracing circuit of claim 1, wherein said mask memory is configured with the corresponding masks prior to the beginning of the functional verification.

8. A method of tracing the change of state of a plurality of signals, wherein each of said signals represents the output resulting from the evaluation of a combinatorial block and/or a plurality of state elements, said combinatorial blocks and/or a plurality of state elements together forming a target design of a functional verification system, the present value of a cluster of said signals being received in pre-specified bit positions of a bus, said bus being shared by a plurality of clusters including said cluster to send corresponding signals, said method comprising:

setting up a mask memory to indicate the bit positions of said bus on which the present value of each of a corresponding cluster of signals is to be received;

storing a previous value for each of said plurality of signals in a previous state memory;

receiving a cluster identifier and a plurality of bits, said cluster identifier identifying the corresponding cluster to which said plurality of bits relate to, said plurality of bits being received on said bus and representing present values for the signals in the cluster identified by said cluster identifier at bit positions indicated by the corresponding mask location;

comparing said plurality of bits with corresponding previous values to determine if there is a change in any of the signal values in said cluster identified by said cluster identifier; and

generating an entry in a trace buffer indicating that change has occurred if a change is detected based on the comparison.

9. The method of claim 8, further comprising wherein each of said mask memory and said previous state memory comprise a number of locations equal to the number of clusters such that said mask memory and said previous state memory can be accessed using said cluster identifier.

10. The method of claim 8, further comprising storing said plurality of bits into said previous state memory to reflect the change in values of corresponding signals if a change is detected.

11. The method of claim 8, further comprising:

receiving a push timer signal; and

generating another entry in said trace buffer responsive to the reception of said push timer signal, wherein said another entry enables the status of different signals to be examined at the time of reception of said push timer signal.

12. A method of tracing the change of state of signals generated in a target design of a functional verification system, said method comprising:

partitioning said target design into a plurality of clusters, each of said plurality of clusters comprising one or more combinatorial blocks;

providing a bus to transfer a present value, wherein said present value represents signals generated by evaluation of said one of more combinatorial blocks contained within a cluster, wherein said bus is shared to transfer present values generated by said plurality of clusters;

storing a previous value for each of said signals;

receiving a cluster identifier and a plurality of bits, said cluster identifier identifying the corresponding cluster to which said plurality of bits relate to, said plurality of bits being received on said bus and representing a present value for the cluster identified by said cluster identifier;

comparing said plurality of bits with corresponding previous values to determine if there is a change in any of the signal values in said cluster identified by said cluster identifier; and

generating an entry indicating that change has occurred if a change is detected based on said comparing.

13. A tracing system for tracing the change of state of signals generated in a target design of a functional verification system, said tracing system comprising:

means for partitioning said target design into a plurality of clusters, each of said plurality of clusters comprising one or more combinatorial blocks;

means for providing a bus to transfer a present value, wherein said present value represents signals generated by evaluation of said one of more combinatorial blocks contained within a cluster, wherein said bus is shared to transfer present values generated by said plurality of clusters;

means for storing a previous value for each of said signals;

means for receiving a cluster identifier and a plurality of bits, said cluster identifier identifying the corresponding cluster to which said plurality of bits relate to, said plurality of bits being received on said bus and representing a present value for the cluster identified by said cluster identifier;

means for comparing said plurality of bits with corresponding previous values to determine if there is a change in any of the signal values in said cluster identified by said cluster identifier; and

means for generating an entry indicating that change has occurred if a change is detected based on said comparing.