Chip on board and heat sink attachment methods

• US 6,630,371 B2
• Filed: 07/02/2002
• Issued: 10/07/2003
• Est. Priority Date: 09/03/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hembree, David R.
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US10/189,097
• Publication Number:
  US 20020177258A1
• Time in Patent Office: 462 Days
• Field of Search: 438/106, 438/127, 438/118, 438/122, 438/759
• US Class Current: 438/118
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85002 being a removable or sacrificial coating
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conducting filled gel elastomer material or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Claims

1. An encapsulation method for a semiconductor die having a surface and a heat sink having a surface comprising:

applying a layer of material as a mask to a portion of said surface of said semiconductor die;

applying an encapsulant material to a remaining portion of said surface of said semiconductor die;

removing said layer of material from said surface of said semiconductor die, said removing including peeling said layer of material from said surface of said semiconductor die; and

securing said heat sink to said surface of said semiconductor die.

2. The method of claim 1, wherein said encapsulant material includes a silicon gel material.

3. The method of claim 2, wherein said silicon gel material includes a gel elastomer material filled with heat conductive particles whereby heat conductivity is enhanced.

4. The method of claim 1, wherein said heat sink is resiliently mounted to said surface of said semiconductor die.

5. A method for encapsulating a chip scale semiconductor package having a surface, a substrate, and a heat sink having a surface comprising:

applying a layer of material as a mask to a portion of said surface of said chip scale semiconductor package;

applying an encapsulant material to a remaining portion of said surface of said chip scale semiconductor package;

removing said layer of material from said surface of said chip scale semiconductor package, said removing including peeling said layer of material from said surface of said chip scale semiconductor package;

bonding said chip scale semiconductor package to said substrate; and

securing said heat sink to said surface of said chip scale semiconductor package.

6. A method for applying a glob top material to a semiconductor die having a surface and a heat sink having a surface comprising:

applying a first layer of material to said surface of said semiconductor die;

applying a second layer of material as a mask to a portion of a surface of said first layer of material;

applying an encapsulant material to a remaining portion of said surface of said semiconductor die;

removing said first layer of material from said surface of said semiconductor die, said removing including peeling said first layer of material from said surface of said semiconductor die; and

securing said heat sink to a surface of said second layer of material.

7. A method for applying a glob top material to a surface of a semiconductor die having a heat sink having a surface comprising:

applying a layer of material as a mask to a portion of said surface of said semiconductor die;

applying glob top material to a remaining portion of said surface of said semiconductor die;

removing said layer of material from said surface of said semiconductor die, said removing including peeling said layer of material from said surface of said semiconductor die; and

securing said heat sink to said surface of said semiconductor die.

8. A method of packing a portion of a Chip On Board semiconductor device having a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, and a plurality of edges;

providing a substrate;

providing a thermally conductive heat sink member;

attaching said first side of said semiconductor die to said substrate;

covering at least a portion of said second side of said semiconductor die with a material having an exposed surface;

applying a material to encapsulate said plurality of edges of said semiconductor die;

maintaining said exposed surface of said material covering at least a portion of said second side of said semiconductor die substantially unencapsulated;

removing said material having an exposed surface covering at least a portion of said second side of said semiconductor die, said removing including peeling said material from said said at least a portion of said second side of said semiconductor die; and

attaching said thermally conductive heat sink member to said second side of said semiconductor die.

9. The method of claim 8, wherein providing said semiconductor die includes providing a semiconductor die having wire bond pads;

and

wirebonding said wire bond pads of said semiconductor die to said substrate.

10. The method of claim 9, wherein said thermally conductive heat sink member is attached to said semiconductor die between said wire bond pads of said semiconductor die.

11. The method of claim 8, wherein providing said semiconductor die includes providing a semiconductor die having a surface having a grid of circuit connections configured for downbonding to said substrate;

and

attaching said semiconductor die to said substrate includes attaching said grid of circuit connections to said substrate.

12. The method of claim 11, wherein said heat sink member is attached to a non-active back side surface of said semiconductor die.

13. The method of claim 8, wherein said substrate is a printed circuit board.

14. The method of claim 8, wherein the step of removing said material includes peeling said material away from said second side of said semiconductor die.

15. The method of claim 8, wherein said covering at least a portion of said second side of said semiconductor die includes covering at least a portion of said second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

16. The method of claim 15, wherein said gel elastomer is filled with metal particles.

17. The method of claim 8, wherein attaching said heat sink member includes attaching said heat sink member to said second side of said semiconductor die with a thermally conductive adhesive.

18. The method of claim 8, wherein attaching said heat sink member includes attaching said heat sink member to said second side of said semiconductor die with a polymeric tape.

19. A method for applying a glob top material to a surface of a semiconductor die having a heat sink having a surface comprising:

applying a layer of gel elastomer material as a mask to a portion of said surface of said semiconductor die;

applying glob top material to a remaining portion of said surface of said semiconductor die;

peeling said gel elastomer material from said surface of said semiconductor die; and

attaching said surface of said heat sink to said surface of said semiconductor die.

20. The method of claim 19, wherein said gel elastomer material includes a gel elastomer material filled with particles.

21. A method for forming a Chip On Board semiconductor device having a heat sink member and a substrate having electrical connections, said method comprising:

providing a semiconductor die having a first side, a second side, a plurality of edges, and electrical terminals;

attaching said first side of said semiconductor die to said substrate;

connecting said electrical terminals of said semiconductor die to said electrical connections of said substrate;

covering at least a portion of said second side of said semiconductor die with a compliant protective layer having an exposed surface;

applying a material to encapsulate said electrical terminals and die edges;

maintaining said exposed surface of said protective layer substantially unencapsulated by said material;

removing said protective layer, said removing including peeling said protective layer; and

attaching said heat sink member to said second side of said semiconductor die.

22. The method of claim 21, wherein said step of providing a semiconductor die includes providing a semiconductor die having wire bond pads;

and

connecting said electrical terminals of said semiconductor die includes wirebonding said electrical terminals of said semiconductor die to said electrical connections of said substrate.

23. The method of claim 22, wherein said heat sink member is attached to said second surface of said semiconductor die between said electrical terminals of said semiconductor die.

24. The method of claim 21, wherein providing said semiconductor die includes providing a semiconductor die having an active surface with a grid of circuit connections configured for bonding to said substrate;

and

connecting said electrical terminals of said semiconductor die to said electrical connections of said substrate includes bonding said grid of circuit connections to said substrate.

25. The method of claim 24, wherein said heat sink member is attached to a non-active back side surface of said semiconductor die.

26. The method of claim 21, wherein said substrate is a printed circuit board.

27. The method of claim 21, wherein removing said protective layer includes peeling said protective layer away from said second side of said semiconductor die.

28. The method of claim 21, wherein covering at least a portion of said second side of said semiconductor die includes covering at least a portion of said second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

29. The method of claim 28, wherein said thermally conductive gel elastomer comprises cross-linked silicone.

30. The method of claim 28, wherein said thermally conductive gel elastomer is filled with metal particles.

31. The method of claim 30, wherein attaching said heat sink member includes attaching said heat sink member to said second side of said semiconductor die with a non-stress thermally conductive adhesive.

32. The method of claim 31, wherein attaching said heat sink member includes attaching said heat sink member to said second side of said semiconductor die with a polymeric tape.

33. A method for forming a semiconductor device assembly having a heat sink, having a semiconductor die having a first side, a second side, and a plurality of edges, and having a substrate, said method comprising:

attaching said first side of said semiconductor die to said substrate;

covering at least a portion of said second side of said semiconductor die with a material having an exposed surface;

applying a material to encapsulate said edges of said semiconductor die;

maintaining said exposed surface of said material covering at least a portion of said second side of said semiconductor die substantially unencapsulated;

removing said material having said exposed surface covering at least a portion of said second side of said semiconductor die, said removing said material including peeling said material away from said second side of said semiconductor die; and

attaching said heat sink to said second side of said semiconductor die.

34. The method of claim 33, wherein said semiconductor die includes a semiconductor die having wire bond pads;

and

wirebonding said wire bond pads of said semiconductor die to said substrate.

35. The method of claim 34, wherein said heat sink is attached to said semiconductor die between said wire bond pads of said semiconductor die.

36. The method of claim 33, wherein said semiconductor die includes a semiconductor die having a surface having a grid of circuit connections configured for downbonding to said substrate;

and

attaching said semiconductor die to said substrate includes attaching said grid of circuit connections to said substrate.

37. The method of claim 36, wherein said heat sink is attached to a non-active back side surface of said semiconductor die.

38. The method of claim 33, wherein said substrate is a printed circuit board.

39. The method of claim 33, wherein said covering at least a portion of said second side of said semiconductor die includes covering at least a portion of said second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

40. The method of claim 39, wherein said thermally conductive gel elastomer comprises cross-linked silicone.

41. The method of claim 40, wherein said thermally conductive gel elastomer is filled with metal particles.

42. The method of claim 33, wherein attaching said heat sink includes attaching said heat sink to said second side of said semiconductor die with a thermally conductive adhesive.

43. The method of claim 33, wherein attaching said heat sink includes attaching said heat sink to said second side of said semiconductor die with a polymeric tape.