Ground plane for exposed package

• US 6,630,373 B2
• Filed: 02/26/2002
• Issued: 10/07/2003
• Est. Priority Date: 02/26/2002
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: ST Assembly Test Services Inc.
• Inventors: Punzalan, Jeffrey D., Han, Byung Joon, Yee, Jae Hak, Zheng, Zheng, Tan, Hien Boon
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US10/083,993
• Publication Number:
  US 20030160309A1
• Time in Patent Office: 588 Days
• Field of Search: 438/123, 438/124, 438/112, 438/127, 257/676, 257/666, 257/691, 257/670
• US Class Current: 438/123
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.

Claims

1. A method of creating a semiconductor device package, comprising the steps of:

providing a semiconductor device;

providing a leadframe, conductive traces having been provided over the surface of said lead frame;

providing a ground plane, said ground plane forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame;

depositing a layer of die attach paste over the surface of said die attach paddle;

mounting said semiconductor device over said layer of die attach paste, thereby mounting said semiconductor device over said die attach paddle;

providing first conductive interconnects between points of electrical contact on an active surface of the semiconductor die and said conductive traces having been provided over the surface of said lead frame;

providing second conductive interconnects between points of electrical contact on an active surface of the semiconductor die and said ground plane; and

providing a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

2. The method of claim 1, said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires.

3. The method of claim 1, said second conductive interconnects comprising ground wires.

4. The method of claim 1, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

5. The method of claim 1, said ground plane comprising an uninterrupted frame spatially surrounding said die attach paddle, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

6. The method of claim 1, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

7. A method of creating a semiconductor device package, comprising the steps of:

providing a semiconductor device;

providing a leadframe, conductive traces having been provided over the surface of said lead frame;

providing a ground plane, said ground plane forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame;

depositing a layer of die attach paste over the surface of said die attach paddle;

mounting said semiconductor device over said layer of die attach paste, thereby mounting said semiconductor device over said die attach paddle;

providing first conductive interconnects between points of electrical contact on an active surface of the semiconductor die and said conductive traces having been provided over the surface of said lead frame, first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires;

providing second conductive interconnects between points of electrical contact on an active surface of the semiconductor die and said ground plane; and

providing a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

8. The method of claim 7, said second conductive interconnects comprising ground wires.

9. The method of claim 7, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

10. The method of claim 7, said ground plane comprising an uninterrupted frame spatially surrounding said die attach paddle, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

11. The method of claim 7, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

12. A method of creating a semiconductor device package, comprising the steps of:

providing a semiconductor device;

providing a leadframe, conductive traces having been provided over the surface of said lead frame;

providing a ground plane, said ground plane forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame;

depositing a layer of die attach paste over the surface of said die attach paddle;

mounting said semiconductor device over said layer of die attach paste, thereby mounting said semiconductor device over said die attach paddle;

providing first conductive interconnects between points of electrical contact on an active surface of the semiconductor die and said conductive traces having been provided over the surface of said lead frame, first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires;

providing second conductive interconnects between points of electrical contact on an active surface of the semiconductor die and said ground plane, said second conductive interconnects comprising ground wires; and

providing a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

13. The method of claim 12, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

14. The method of claim 12, said ground plane comprising an uninterrupted frame spatially surrounding said die attach paddle, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

15. The method of claim 12, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle, said ground plane comprising a square or rectangular geometric shape when viewed in top view.