Low temperature silicon wafer bond process with bulk material bond strength

• US 6,630,713 B2
• Filed: 02/25/1999
• Issued: 10/07/2003
• Est. Priority Date: 11/10/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Geusic, Joseph E.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Peralta, Ginette
• Application Number:
  US09/257,659
• Publication Number:
  US 20010014514A1
• Time in Patent Office: 1,685 Days
• Field of Search: 438/455, 257/347, 257/549, 257/550, 257/635, 257/51, 257/74
• US Class Current: 257/347
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/76251 using bonding techniques

Abstract

The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.

Claims

1. A semiconductor device comprising:

a first semiconductor wafer and a second semiconductor wafer, each having an annular edge, the second wafer laser treated and bonded annealed to the first semiconductor wafer forming Si—

Si bonding, wherein the bond is substantially free of hydrogen or defects; and

an integrated circuit element that is adjacent to wafer surface, positioned on or within the annular edge of one of the semiconductor wafers and the Si—

Si bond the integrated circuit element comprising one or more of aluminum, copper, polysilicon and gold.

2. The semiconductor device of claim 1 wherein the semiconductor wafers have a diameter of about 4 inches.

3. The semiconductor article of claim 1 and further comprising germanium wherein the article is bonded to germanium to form a sensor.

4. The semiconductor article of claim 1 and further comprising germanium wherein the article is bonded to germanium to form a fiber optic element.

5. The semiconductor article of claim 1 and further comprising a gallium arsenide circuit integrated with the circuit on the silicon.

6. The semiconductor article of claim 5 wherein the gallium arsenide comprises a diffusion barrier comprising silicon dioxide, tungsten, or ceramic.

7. A valve comprising the semiconductor article of claim 6.

8. The semiconductor article of claim 1 and further comprising a laser circuit integrated with the circuit on the silicon.

9. A sensor comprising the article of claim 1.

10. A fiber optic element comprising the article of claim 1.

11. A light emitting diode comprising the article of claim 1.

12. A surface emitting laser comprising the article of claim 1.

13. The article of claim 1 and further comprising an insulator hardened by radiation.

14. A semiconductor device comprising:

a first silicon wafer and a second silicon wafer laser bonded by Si—

Si bonds to the first silicon wafer; and

a circuit element positioned on or within the second silicon wafer and the Si—

Si bond that comprises one or more of aluminum, copper, polysilicon, and gold wherein the aluminum, copper, polysilicon and gold are free of any laser bonding temperature changes and wherein the circuit element is adjacent to silicon.

15. The semiconductor of claim 14 wherein each of the bonded wafers has a surface that is available for use over its entirety.

16. A semiconductor article comprising a p-type silicon wafer and an n-type silicon wafer wherein the p-type silicon wafer is laser bonded by Si—

Si bonds to the n-type silicon wafer and is substantially free of hydrogen or defects.

17. The semiconductor article of claim 16 wherein the p-type wafer and the n-type wafer have substantially the same crystallographic structure.

18. The semiconductor article of claim 16 wherein the orientations of the p-type wafer and the n-type wafer are aligned within approximately one degree.

19. The semiconductor article of claim 16 and further including a P-N junction.

20. The semiconductor article of claim 16 wherein the wafers are free from an oxide layer formed at a junction of the wafers.

21. A NMOS transistor comprising the article of claim 20.

22. A PMOS transistor comprising the article of claim 20.

23. A light emitting diode comprising the article of claim 20.

24. A surface emitting laser comprising the article of claim 20.

25. The article of claim 16 and further comprising an insulator hardened by radiation.

26. A device for use in space comprising the article of claim 25.