Gate dielectric antifuse circuits and methods for operating same

• US 6,630,724 B1
• Filed: 08/31/2000
• Issued: 10/07/2003
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W.
• Primary Examiner(s): Ngô, Ngân V.
• Application Number:
  US09/652,429
• Time in Patent Office: 1,132 Days
• Field of Search: 257/530, 365/189.05, 365/189.09, 365/225.7
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.

Claims

1. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;

a common bus line driver circuit to couple the common bus line to a reference voltage during an active mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

2. The integrated circuit of claim 1 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a first high-voltage transistor and a first control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the common bus line driver circuit comprises a second high-voltage transistor and a second control transistor coupled in series between the common bus line and a ground voltage;

the read circuit comprises a transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during the active mode;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistor and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

3. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

coupling the common bus line to a voltage reference with a common bus line driver circuit during an active mode;

reading the antifuse during the active mode with a read circuit coupled to the second terminal of the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

switching off transistors in the read circuit and the latch circuit during the programming mode with a floating well driver logic circuit coupled to the read circuit and the latch circuit.

4. The method of claim 3 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprises switching on a first control transistor coupled in series with a first high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

coupling the common bus line to a voltage reference further comprises switching on a second control transistor to couple the common bus line to a ground voltage through a second high-voltage transistor and the second control transistor coupled together in series;

reading the antifuse further comprises coupling the ground voltage to the first terminal of the antifuse, coupling a read voltage to the second terminal of the antifuse through a transistor, and detecting a voltage of the second terminal of the antifuse to read the antifuse;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistor; and

switching off transistors in the read circuit and the latch circuit further comprises raising a voltage of a gate terminal and a well of a p-channel transistor to substantially prevent current in the p-channel transistor.

5. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a common bus line driver circuit to couple the common bus line to a voltage reference during an active mode, the commmon bus line driver circuit comprising;

a first high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal;

a diode coupled between the control terminal and a voltage reference; and

a first control transistor coupled between the second terminal of the high-voltage transistor and a voltage reference;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

6. The integrated circuit of claim 5 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a second high-voltage transistor and a second control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the read circuit comprises a transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during the active mode;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors;

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor;

the first high-voltage transistor comprises an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to the diode, and a source terminal coupled to the first control transistor;

the diode comprises;

a first diode comprising an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor; and

a second diode comprising a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a voltage reference to withstand a high voltage on the control terminal of the n-well drain transistor; and

the first control transistor is coupled between the source terminal of the n-well drain transistor and a ground voltage to couple the common bus line to the ground voltage when the first control transistor is switched on and to permit the elevated voltage on the common bus line when the first control transistor is switched off.

7. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

switching off a first control transistor in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line through the common bus line driver circuit during the programming mode;

bearing a portion of the elevated voltage across a first high-voltage transistor in the common bus line driver circuit, the first high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal coupled to the first control transistor during the programming mode;

bearing a portion of the elevated voltage between a diode and the control terminal of the first high-voltage transistor during the programming mode;

switching on the first control transistor to couple the common bus line to the voltage reference during an active mode;

reading the antifuse during the active mode with a read circuit coupled to the second terminal of the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

switching off transistors in the read circuit and the latch circuit during the programming mode with a floating well driver logic circuit coupled to the read circuit and the latch circuit.

8. The method of claim 7 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprises switching on a second control transistor coupled in series with a second high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

reading the antifuse comprises coupling a ground voltage to the first terminal of the antifuse, coupling a read voltage to the second terminal of the antifuse through a transistor, and detecting a voltage of the second terminal of the antifuse to read the antifuse;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistors;

switching off transistors in the read circuit and the latch circuit further comprises raising a voltage of a gate terminal and a well of a p-channel transistor to substantially prevent current in the p-channel transistor;

switching off a first control transistor further comprises switching off the first control transistor comprising an n-channel transistor;

bearing a portion of the elevated voltage across a first high-voltage transistor further comprises bearing a portion of the elevated voltage across an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to the diode, and a source terminal coupled to the first control transistor; and

bearing a portion of the elevated voltage between a diode and the control terminal further comprises bearing a portion of the elevated voltage between the control terminal of the n-well drain transistor, a first diode comprising an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor, and a second diode comprising a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a voltage reference.

9. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a common bus line driver circuit to couple the common bus line to a voltage reference during an active mode;

a read circuit comprising a read transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

10. The integrated circuit of claim 9 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between a first terminal and the second terminal of the antifuse;

the program driver circuit comprises a first high-voltage transistor and a first control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the common bus line driver circuit comprises a second high-voltage transistor and a second control transistor coupled in series between the common bus line and a ground voltage;

the read transistor comprises a p-channel transistor having a source terminal coupled to the read voltage and a gate terminal coupled to a bias voltage;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

11. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

coupling the common bus line to a voltage reference with a common bus line driver circuit during an active mode;

reading the antifuse with a read circuit during the active mode comprising;

coupling a read voltage to the second terminal of the antifuse through a read transistor; and

detecting a voltage of the second terminal of the antifuse to read the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

switching off transistors in the read circuit and the latch circuit during the programming mode with a floating well driver logic circuit coupled to the read circuit and the latch circuit.

12. The method of claim 11 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprises switching on a first control transistor coupled in series with a first high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

coupling the common bus line to a voltage reference further comprises switching on a second control transistor to couple the common bus line to a ground voltage through a second high-voltage transistor and the second control transistor coupled together in series;

coupled a read voltage further comprises coupling the read voltage to the second terminal of the antifuse through a p-channel transistor switched on by a bias voltage;

detecting a voltage further comprises detecting the voltage of the second terminal of the antifuse with an input of an inverter during the active mode;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistor; and

switching off transistors in the read circuit and the latch circuit further comprises raising a voltage of a gate terminal and a well of a p-channel transistor of substantially prevent current in the p-channel transistor.

13. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a common bus line driver circuit to couple the common bus line to a voltage reference during an active mode;

a read circuit comprising a p-channel transistor coupled between a read voltage source and the second terminal of the antifuse to couple the read voltage source to the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to a gate terminal and a well of the p-channel transistor to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

14. The integrated circuit of claim 13 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a first high-voltage transistor and a first control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the common bus line driver circuit comprises a second high-voltage transistor and a second control transistor coupled in series between the common bus line and a ground voltage;

the read circuit further comprises a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistor and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a voltage source coupled to a gate terminal and a well of selected ones of the p-channel transistors in the read circuit to raise a voltage of the gate terminals and the wells during the programming mode to substantially prevent current in the selected p-channel transistors.

15. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

coupling the common bus line to a voltage reference with a common bus line driver circuit during an active mode;

reading the antifuse during the active mode with a p-channel transistor in a read circuit coupled between a read voltage source and the second terminal of the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

raising a voltage of a gate terminal and a well of the p-channel transistor during the programming mode to substantially prevent current in the p-channel transistor.

16. The method of claim 15 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprises switching on a first control transistor coupled in series with a first high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

coupling the common bus line to a voltage reference further comprises switching on a second control transistor to couple the common bus line to a ground voltage through a second high-voltage transistor and the second control transistor coupled together in series;

reading the antifuse further comprises detecting a voltage of the second terminal of the antifuse with an inverter in the read circuit;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistors; and

raising a voltage further comprises coupling a rising voltage of the second terminal of the antifuse to a gate terminal and a well of each of a plurality of p-channel transistors in the read circuit.

17. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a common bus line driver circuit to couple the common bus line to a voltage reference during an active mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

means for switching off transistors in the read circuit and the latch circuit during the programming mode.

18. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a common bus line driver circuit to couple the common bus line to a voltage reference during an active mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

19. The integrated circuit of claim 18 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a first high-voltage transistor and a first control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the common bus line driver circuit comprises a second high-voltage transistor and a second control transistor coupled in series between the common bus line and a ground voltage;

the read circuit comprises a transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during the active mode;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

20. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during an active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

21. The integrated circuit of claim 20 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the read circuit comprises a transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during the active mode;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

22. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

reading the antifuse during an active mode with a read circuit coupled to the second terminal of the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

switching off transistors in the read circuit and the latch circuit during the programming mode with a floating well driver logic circuit coupled to the read circuit and the latch circuit.

23. The method of claim 22 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprises switching on a control transistor coupled in series with a high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

reading the antifuse further comprises coupling the ground voltage to the first terminal of the antifuse, coupling a read voltage to the second terminal of the antifuse through a transistor, and detecting a voltage of the second terminal of the antifuse to read the antifuse;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistors; and

switching off transistors in the read circuit and the latch circuit further comprises raising a voltage of a gate terminal and a well of a p-channel transistor to substantially prevent current in the p-channel transistor.

24. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a read circuit comprising a read transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during an active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

25. The integrated circuit of claim 24 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the read transistor comprises a p-channel transistor having a source terminal coupled to the read voltage and a gate terminal coupled to a bias voltage;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

26. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

reading the antifuse with a read circuit during an active mode comprising;

coupling a read voltage to the second terminal of the antifuse through a read transistor; and

detecting a voltage of the second terminal of the antifuse to read the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

switching off transistors in the read circuit and the latch circuit during the programming mode with a floating well driver logic circuit coupled to the read circuit and the latch circuit.

27. The method of claim 26 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprising switching on a control transistor coupled in series with a high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

coupling a read voltage further comprises coupling the read voltage to the second terminal of the antifuse through a p-channel transistor switched on by a bias voltage;

detecting a voltage further comprises detecting the voltage of the second terminal of the antifuse with an input of an inverter during the active mode;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistors; and

switching off transistors in the read circuit and the latch circuit further comprises raising a voltage of a gate terminal and a well of a p-channel transistor to substantially prevent current in the p-channel transistor.

28. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a read circuit comprising a p-channel transistor coupled between a read voltage source and the second terminal of the antifuse to couple the read voltage source to the antifuse to read the antifuse during an active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to a gate terminal and a well of the p-channel transistor to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.

29. The integrated circuit of claim 28 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the read circuit further comprises a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit;

the latch circuit comprises an inverter having in input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a voltage source coupled to a gate terminal and a well of selected ones of the p-channel transistors in the read circuit to raise a voltage of the gate terminals and the wells during the programming mode to substantially prevent current in the selected p-channel transistors.

30. A method of operating an integrated circuit comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and a first terminal of an antifuse to program the antifuse with the elevated voltage during a programming mode;

selecting the antifuse to be programmed during the programming mode with a program driver circuit coupled to a second terminal of the antifuse;

reading the antifuse duringan active mode with a p-channel transistor in a read circuit coupled between a read voltage source and the second terminal of the antifuse;

latching a state of the antifuse during a sleep mode with a latch circuit coupled to the second terminal of the antifuse; and

raising a voltage of a gate terminal and a well of the p-channel transistor during the programming mode to substantially prevent current in the p-channel transistor.

31. The method of claim 30 wherein:

coupling an elevated voltage to an external pin further comprises coupling the elevated voltage to terminals of a plurality of antifuses coupled to the common bus line in an antifuse bank;

selecting the antifuse to be programmed further comprises switching on a control transistor coupled in series with a high-voltage transistor between the second terminal of the antifuse and a ground voltage, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse;

reading the antifuse further comprises detecting a voltage of the second terminal of the antifuse with an inverter in the read circuit;

latching a state of the antifuse further comprises latching the voltage of the second terminal of the antifuse with a latch circuit including an inverter and a plurality of latch transistors; and

raising a voltage further comprises coupling a rising voltage of the second terminal of the antifuse to a gate terminal and a well of each of a plurality of p-channel transistors in the read circuit.

32. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a read coupled to the second terminal of the antifuse to read the antifuse during an active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

means for switching off transistors in the read circuit and the latch circuit during the programming mode.

33. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse during a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during the programming mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during an active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

34. The integrated circuit of claim 33 wherein:

the common bus line is coupled to terminals of a plurality of antifuses in an antifuse bank;

the antifuse comprises a gate dielectric between the first terminal and the second terminal of the antifuse;

the program driver circuit comprises a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage;

the read circuit comprises a transistor coupled between a read voltage and the second terminal of the antifuse to couple the read voltage to the antifuse to read the antifuse during the active mode;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

the floating well driver logic circuit further comprises a circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor.