Three-dimensional memory array incorporating serial chain diode stack

• US 6,631,085 B2
• Filed: 06/29/2001
• Issued: 10/07/2003
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Lee, Thomas H., Johnson, Mark G., Kleveland, Bendik, Knall, N. Johan
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/897,705
• Publication Number:
  US 20030053332A1
• Time in Patent Office: 830 Days
• Field of Search: 365/96, 365/105, 365/175, 365/243, 257/50, 257/209, 257/211, 257/539, 257/928, 438/131
• US Class Current: 365/175
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N² memory cells, rather than approximately 3N² memory cells as with prior arrays.

Claims

1. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of conductors on at least three levels of the memory array, forming a passive element memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality;

wherein the respective directionality of memory cells on at least two adjacent levels are oriented alike; and

wherein memory cells in at least one pair of adjacent memory planes share conductors disposed between said pair of adjacent memory planes.

2. The integrated circuit defined by claim 1 wherein:

the conductors at each level comprise a plurality of parallel, spaced-apart rail-stacks.

3. The integrated circuit defined by claim 1 further comprising:

programming circuits for driving a selected conductor on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected conductor, and to a second programming voltage if the selected memory plane is disposed below the selected conductor.

4. The integrated circuit defined by claim 1 further comprising:

high-voltage drivers for the conductors of at least one level capable of passing a write current in either direction depending on the directionality of a selected memory cell.

5. The integrated circuit defined by claim 1 wherein the memory cells comprise a semiconductor material.

6. The integrated circuit defined by claim 1 wherein the memory cells comprise an organic polymer.

7. The integrated circuit defined by claim 1 wherein the memory cells comprise a phase change material.

8. The integrated circuit defined by claim 1 wherein the memory cells comprise an amorphous solid.

9. The integrated circuit defined by claim 5 wherein the memory cells comprise an antifuse layer.

10. The integrated circuit defined by claim 5 wherein the memory cells comprise a fuse layer.

11. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of parallel, spaced-apart conductors on each level of the memory array, forming memory cells at each intersection between conductors of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;

wherein the respective directionality of memory cells in at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed; and

wherein memory cells in at least one pair of adjacent memory planes share conductors disposed between said pair of adjacent memory planes.

12. The integrated circuit defined by claim 11 wherein:

the conductors at each level comprise a plurality of parallel, spaced-apart rail-stacks.

13. The integrated circuit defined by claim 11 further comprising:

programming circuits for driving a selected conductor on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected conductor, and to a second programming voltage if the selected memory plane is disposed below the selected conductor.

14. The integrated circuit defined by claim 11 further comprising:

high-voltage drivers for the conductors of at least one level capable of passing a write current in either direction depending on the directionality of a selected memory cell.

15. The integrated circuit defined by claim 11 wherein the memory cells comprise a semiconductor material.

16. The integrated circuit defined by claim 11 wherein the memory cells comprise an organic polymer.

17. The integrated circuit defined by claim 11 wherein the memory cells comprise a phase change material.

18. The integrated circuit defined by claim 11 wherein the memory cells comprise an amorphous solid.

19. The integrated circuit defined by claim 11 wherein the memory cells comprise an antifuse layer.

20. The integrated circuit defined by claim 11 wherein the memory cells comprise a fuse layer.

21. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of parallel, spaced-apart rail-stacks on each level of the memory array, forming memory cells at each intersection between rail-stacks of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;

wherein the respective directionality of memory cells in at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed; and

wherein memory cells in at least one pair of adjacent memory planes share rail-stacks disposed between said pair of adjacent memory planes.

22. The array defined by claim 21, further comprising:

programming circuits for driving a selected rail-stack on a level of the memory array to a first programming voltage if the selected rail-stack is connected to a selected memory cell anode terminal, and to a second programming voltage if the selected rail-stack is connected to a selected memory cell cathode terminal.

23. The array defined by claim 21 further comprising:

programming circuits for driving a selected rail-stack on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected rail-stack, and to a second programming voltage if the selected memory plane is disposed below the selected rail-stack.

24. The integrated circuit defined by claim 22 wherein the memory cells comprise an antifuse layer.

27. The integrated circuit defined by claim 21 wherein the memory cells comprise a semiconductor material.

28. The integrated circuit defined by claim 21 wherein the memory cells comprise an organic polymer.

29. The integrated circuit defined by claim 21 wherein the memory cells comprise a phase change material.

30. The integrated circuit defined by claim 21 wherein the memory cells comprise an amorphous solid.

31. The integrated circuit defined by claim 27 wherein the memory cells comprise an antifuse layer.

32. The integrated circuit defined by claim 27 wherein the memory cells comprise a fuse layer.

25. An integrated circuit comprising:

a three-dimensional memory array including alternating levels of X-lines and Y-lines forming passive element memory cells at each intersection between X-lines of one level and Y-lines of an adjacent level, each cell having an anode terminal and a cathode terminal; and

X-line circuitry for driving, during a write mode, a selected X-line associated with a selected memory plane to a first voltage, and unselected X-lines associated with the selected memory plane to a second voltage if the X-lines associated with the selected memory plane are coupled to the respective anode terminals of the selected plane memory cells, and for driving, during the write mode, a selected X-line associated with the selected memory plane to a third voltage and for driving unselected X-lines associated with the selected memory plane to a fourth voltage if the X-lines associated with the selected memory plane are coupled to the respective cathode terminals of the selected plane memory cells.

26. The array defined by claim 25 further comprising:

Y-line circuitry for driving, during a write mode, a selected Y-line associated with a selected memory plane to a first voltage, and unselected Y-lines associated with the selected memory plane to a second voltage if the Y-lines associated with the selected memory plane are coupled to the respective anode terminals of the selected plane memory cells, and for driving, during the write mode, a selected Y-line associated with the selected memory plane to a third voltage and for driving unselected Y-lines associated with the selected memory plane to a fourth voltage if the Y-lines associated with the selected memory plane are coupled to the respective cathode terminals of the selected plane memory cells.

33. The integrated circuit defined by claim 25 wherein the memory cells comprise a semiconductor material.

34. The integrated circuit defined by claim 25 wherein the memory cells comprise an organic polymer.

35. The integrated circuit defined by claim 25 wherein the memory cells comprise a phase change material.

36. The integrated circuit defined by claim 25 wherein the memory cells comprise an amorphous solid.

37. The integrated circuit defined by claim 33 wherein the memory cells comprise an antifuse layer.

38. The integrated circuit defined by claim 33 wherein the memory cells comprise a fuse layer.

39. An integrated circuit comprising:

a three-dimensional memory array including

alternating levels of X-lines and Y-lines;

plural memory planes, each plane comprising passive element memory cells formed respectively at intersections between X-lines of one level and Y-lines of an adjacent level, each memory cell having a respective directionality;

wherein at least two adjacent memory planes are both associated with the respective level of X-lines or Y-lines disposed therebetween; and

wherein the respective directionalities of memory cells on said at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.

40. The integrated circuit defined by claim 39 wherein the memory cells comprise a semiconductor material.

41. The integrated circuit defined by claim 39 wherein the memory cells comprise an organic polymer.

42. The integrated circuit defined by claim 39 wherein the memory cells comprise a phase change material.

43. The integrated circuit defined by claim 39 wherein the memory cells comprise an amorphous solid.

44. The integrated circuit defined by claim 40 wherein the memory cells comprise an antifuse layer.

45. The integrated circuit defined by claim 40 wherein the memory cells comprise a fuse layer.

46. The integrated circuit defined by claim 39 wherein:

the X-lines or Y-lines at each level comprise a plurality of parallel, spaced-apart rail-stacks.

47. The integrated circuit defined by claim 39 further comprising:

programming circuits for driving a selected X-line or Y-line on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected X-line or Y-line, and to a second programming voltage if the selected memory plane is disposed below the selected X-line or Y-line.

48. The integrated circuit defined by claim 39 further comprising:

high-voltage drivers for the X-lines or Y-lines of at least one level capable of passing a write current in either direction depending on the directionality of a selected memory cell.

49. An integrated circuit comprising a three-dimensional memory array including at least two adjacent memory planes of passive element memory cells, each of said two adjacent memory planes associated with a single level of conductors disposed therebetween, memory cells of said two adjacent memory planes having a respective directionality oriented alike.

50. The integrated circuit defined by claim 49 wherein:

the memory array includes at least three levels of conductors and at least two memory planes of passive element memory cells formed at intersections between conductors of adjacent levels; and

at least two adjacent memory planes comprise memory cells having a respective directionality that is oriented in the same direction relative to a substrate upon which the array is formed.

51. The integrated circuit defined by claim 50 comprising antifuse memory cells.

52. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of conductors on at least three levels of the memory array, forming a passive element memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality; and

programming circuits for driving a selected conductor on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected conductor, and to a second programming voltage if the selected memory plane is disposed below the selected conductor;

wherein the respective directionality of memory cells on at least two adjacent levels are oriented alike.

53. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of parallel, spaced-apart conductors on each level of the memory array, forming memory cells at each intersection between conductors of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell; and

programming circuits for driving a selected conductor on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected conductor, and to a second programming voltage if the selected memory plane is disposed below the selected conductor;

wherein the respective directionality of memory cells on at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.

54. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of parallel, spaced-apart rail-stacks on each level of the memory array, forming memory cells at each intersection between rail-stacks of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell; and

programming circuits for driving a selected rail-stack on a level of the memory array to a first programming voltage if the selected rail-stack is connected to a selected memory cell anode terminal, and to a second programming voltage if the selected rail-stack is connected to a selected memory cell cathode terminal;

wherein the respective directionality of memory cells on at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.

55. The integrated circuit defined by claim 54 wherein the memory cells comprise an antifuse layer.

56. An integrated circuit comprising:

a multi-level programmable memory array comprising a plurality of parallel, spaced-apart rail-stacks on each level of the memory array, forming memory cells at each intersection between rail-stacks of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell; and

programming circuits for driving a selected rail-stack on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected rail-stack, and to a second programming voltage if the selected memory plane is disposed below the selected rail-stack;

wherein the respective directionality of memory cells on at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.