Semaphore coding method to ensure data integrity in a can microcontroller and a can microcontroller that implements this method

• US 6,631,431 B1
• Filed: 12/30/1999
• Issued: 10/07/2003
• Est. Priority Date: 09/15/1999
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hank, Peter, Muth, Mathius, Silvkoff, William J., Birns, Neil E.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/474,903
• Time in Patent Office: 1,377 Days
• Field of Search: 710/100, 710/22, 710/308, 709/223, 709/250, 709/229, 370/245, 370/901, 370/908
• US Class Current: 710/100
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: H04L 1/1664 the supervisory signal being transmitted together with payload signals; piggybacking
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2001/0094 Bus
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core and hardware external to the processor core (e.g., a DMA engine) that writes message data into a designated message buffer for ensuring integrity of the message data stored in the designated message buffer. The method includes providing a three-state semaphore to indicate a current access status of the designated message buffer, the three-state semaphore having a first state indicative of the hardware external to the processor core starting to write new message data into the designated message buffer, a second state indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer, and, a third state indicative of the processor core starting to read message data from the designated message buffer. The processor core determines whether the designated message buffer is ready to be accessed based on the current state of the semaphore. The processor core, after determining that the designated message buffer is ready to be accessed, reads the message data from the designated message buffer. After the processor core has finished reading the message data from the designated message buffer, it checks the current state of the semaphore to determine whether it has changed to a different state during the time that the processor core was reading the message data from the designated message buffer. If the processor core determines that the current state of the semaphore changed during the time that the processor core was reading the message data from the designated message buffer, it again determines whether the designated message buffer is ready to be accessed, based on the current state of the semaphore. After again determining that the designated message buffer is ready to be accessed, the processor core again reads the message data from the designated message buffer.

Claims

1. In a CAN (controller area network) device that includes a microcontroller having a processor core and hardware external to the processor core that includes a CAL/CAN hardware module that emulates CAN Application Layer (CAL) software functions by writing message data into a designated message buffer, a method for ensuring integrity of the message data stored in the designated message buffer of the CAL/CAN hardware module, the method including the steps of:

the processor core reads from the designated message buffer a coded semaphore written by a DMA engine of the CAL/CAN module without previous processor core intervention, to indicate a current access status of the designated message buffer, and

the processor core determines whether the designated message buffer is ready to be accessed by the processor core and is not in use by the CAL/CAN module based on a current code value of the coded semaphore.

2. The method as set forth in claim 1, wherein the message data comprises a CAN Frame.

3. The method as set forth in claim 1, wherein the message data comprises a non-fragmented CAN message.

4. The method as set forth in claim 1, wherein the CAN device comprises a CAN microcontroller.

5. The method as set forth in claim 1, further including the step of the hardware external to the processor core determining whether the processor core is currently accessing the designated message buffer, based on a current code value of the coded semaphore.

6. The method as set forth in claim 1, further including the steps of:

the processor core, after determining that the designated message buffer is ready to be accessed, reading the message data from the designated message buffer, and,

the processor core, after it has finished reading the message data from the designated message buffer, checking the current code value of the coded semaphore to determine whether it has changed to a different code value during the time that the processor core was reading the message data from the designated message buffer.

7. The method as set forth in claim 6, further including the steps of:

the processor core, after determining that the current code value of the coded semaphore changed during the time that the processor core was reading the message data from the designated message buffer, again determining whether the designated message buffer is ready to be accessed based on a current code value of the coded semaphore; and

,

the processor core, after again determining that the designated message buffer is ready to be accessed, again reading the message data from the designated message buffer.

8. The method as set forth in claim 1, wherein the coded semaphore comprises a two-bit, three-state semaphore.

9. The method as set forth in claim 8, wherein the three states of the coded semaphore include:

a first state that corresponds to a first code value indicative of the hardware external to the processor core starting to write new message data into the designated message buffer;

a second state that corresponds to a second code value indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer; and

,

a third state that corresponds to a third code value indicative of the processor core starting to read message data from the designated message buffer.

10. The method as set forth in claim 1, wherein the hardware external to the processor core includes a DMA engine.

11. The method as set forth in claim 9, wherein the providing step comprises:

the hardware external to the processor core writing the first code value of the coded semaphore to a designated storage location when it is starting to write new message data into the designated message buffer;

the hardware external to the processor core writing the second code value of the coded semaphore to the designated storage location when it is finished writing new message data into the designated message buffer; and

,

the processor core writing the third code value of the coded semaphore to the designated storage location when it is starting to read message data from the designated message buffer.

12. The method as set forth in claim 11, wherein the designated storage location comprises prescribed bit positions of a first byte of the designated message buffer.

13. The method as set forth in claim 1, wherein the hardware external to the processor core includes a DMA engine.

23. The method as set forth in claim 11, wherein the designated storage location comprises prescribed bit positions of a first byte of the designated message buffer.

25. A CAN device that implements the method set forth in claim 1.

26. The CAN device as set forth in claim 25, wherein the CAN device comprises a CAN microcontroller.

14. In a CAN (controller area network) device that includes a microcontroller having a processor core and hardware external to the processor core that includes a CAL/CAN hardware module that emulates CAN Application Layer (CAL) software functions by writing message data into a designated message buffer, the method including the steps of:

reading a three-state semaphore from the designated message buffer that is written by a DMA engine of the CAL/CAN hardware module without previous processor core intervention to indicate a current access status of the designated message buffer, the three-state semaphore having a first state indicative of the hardware external to the processor core starting to write new message data into the designated message buffer, a second state indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer, and, a third state indicative of the processor core starting to read message data from the designated message buffer; and

the processor core determining whether the designated message buffer is ready to be accessed based on the current state of the semaphore.

15. The method as set forth in claim 14, wherein the message data comprises a CAN Frame.

16. The method as set forth in claim 14, wherein the message data comprises a non-fragmented CAN message.

17. The method as set forth in claim 14, wherein the CAN device comprises a CAN microcontroller.

18. The method as set forth in claim 14, further including the steps of:

the processor core, after determining that the designated message buffer is ready to be accessed, reading the message data from the designated message buffer, and,

the processor core, after it has finished reading the message data from the designated message buffer, checking the current state of the semaphore to determine whether it has changed to a different state during the time that the processor core was reading the message data from the designated message buffer.

19. The method as set forth in claim 18, further including the steps of:

the processor core, after determining that the current state of the semaphore changed during the time that the processor core was reading the message data from the designated message buffer, again determining whether the designated message buffer is ready to be accessed based on the current state of the semaphore; and

,

the processor core, after again determining that the designated message buffer is ready to be accessed, again reading the message data from the designated message buffer.

20. The method as set forth in claim 19, wherein the providing step comprises:

the hardware external to the processor core writing a first code value corresponding to the first state of the semaphore to a designated storage location when it is starting to write new message data into the designated message buffer;

the hardware external to the processor core writing a second code value corresponding to the second state of the semaphore to the designated storage location when it is finished writing new message data into the designated message buffer; and

,

the processor core writing a third code value corresponding to the third state of the semaphore to the designated storage location when it is starting to read message data from the designated message buffer.

21. The method as set forth in claim 20, wherein the designated storage location comprises prescribed bit positions of a first byte of the designated message buffer.

22. The method as set forth in claim 20, wherein the hardware external to the processor core includes a DMA engine.

24. The method as set forth in claim 20, wherein the designated storage location comprises a prescribed storage location within the designated message buffer.

27. A CAN device that implements the method set forth in claim 14.

28. The CAN device as set forth in claim 27, wherein the CAN device comprises a CAN microcontroller.