Cache coherence unit for interconnecting multiprocessor nodes having pipelined snoopy protocol

• US 6,631,448 B2
• Filed: 03/12/1998
• Issued: 10/07/2003
• Est. Priority Date: 03/12/1998
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Weber, Wolf-Dietrich
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US09/041,568
• Publication Number:
  US 20010013089A1
• Time in Patent Office: 2,035 Days
• Field of Search: 711/141, 711/144, 711/145, 711/146, 711/119, 709/213, 709/216, 709/218, 709/251
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

The present invention consists of a cache coherence protocol within a cache coherence unit for use in a data processing system. The data processing system is comprised of multiple nodes, each node having a plurality of processors with associated caches, a memory, and input/output. The processors within the node are coupled to a memory bus operating according to a “snoopy” protocol. This invention includes a cache coherence protocol for a sparse directory in combination with the multiprocessor nodes. In addition, the invention has the following features: the current state and information from the incoming bus request are used to make an immediate decision on actions and next state; the decision mechanism for outgoing coherence is pipelined to follow the bus; and the incoming coherence pipeline acts independently of the outgoing coherence pipeline.

Claims

1. A cache coherence unit for use in a data processing system having multiple nodes, each node having a plurality of processors coupled to a memory bus operating according to a cache coherence protocol, each processor having an associated cache memory for caching data, the cache coherence unit comprising:

a bus interface element coupled to said memory bus;

a coherence control element coupled to said bus interface element and coupled to said cache memories;

a sparse directory coupled to said coherence control element for storing node identifications and information of locations in said cache memories; and

a protocol decision pipeline coupled to said coherence control element for processing concurrent requests for cache memory.

2. The cache coherence unit of claim 1, wherein the coherence control element and the sparse directory have incoming and outgoing ports.

3. The cache coherence unit of claim 1, wherein the sparse directory stores state information characterizing a current transient state and other transient states.

4. The cache coherence unit of claim 3, wherein said coherence control element updates said information characterizing the current transient state.

5. The cache coherence unit of claim 3, wherein said coherence control element updates said information characterizing the current transient state and then updates said information characterizing other transient states.

6. The cache coherence unit of claim 1, wherein said coherence control element comprises:

means for updating information characterizing a current transient state,

means for reading information characterizing other transient states, and

means for updating said information characterizing other transient states after said information characterizing the current transient state has been updated.

7. The cache coherence unit of claim 1, being capable of:

concurrently handling multiple memory bus requests; and

concurrently handling multiple network request.