Temperature programmable timing delay system

• US 6,631,503 B2
• Filed: 01/05/2001
• Issued: 10/07/2003
• Est. Priority Date: 01/05/2001
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Joshi, Rajiv V., Fifield, John A.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LEVIN, NAUM B
• Application Number:
  US09/755,860
• Publication Number:
  US 20020133789A1
• Time in Patent Office: 1,005 Days
• Field of Search: 716/4-6, 702/130, 702/132, 374/170, 374/178, 363/41, 327/276, 327/336, 327/539, 327/543, 324/760, 713/320, 713/322
• US Class Current: 716/136
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: H03K 2005/00143 Avoiding variations of delay due to temperature
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value. A method is also provided for varying a characteristic of a timing delay signal in accordance with variations of the on-chip temperature of an integrated circuit chip. The method includes the steps of generating a reference parameter; sensing the on-chip temperature of the integrated circuit chip by utilizing at least the reference parameter; providing the sensed on-chip temperature as a binary reading; using the binary reading for providing a respective binary code indicating a timing delay; and varying the characteristic of the timing delay signal, such as the signal'"'"'s rise time, in accordance with the binary code.

Claims

1. A temperature programmable timing delay system comprising:

means for generating a reference parameter, wherein said means for generating said reference parameter includes a reference circuit comprising;

a first and a second diode, where said second diode is connected in series with a first resistor,

a first amplifier having a positive input connected to said first resistor and a negative input connected to said first diode, said first amplifier having an output outputting a current output, said output being connected to at least a first set of transistors; and

a second amplifier having a negative input connected to said first diode and a positive input connected to a second resistor, said second amplifier having an output outputting a current output, said output being connected to at least a second set of transistors;

means for sensing the on-chip temperature by utilizing at least said reference parameter; and

means for providing a timing adjustment signal for adjusting a clock rate corresponding to an output of said means for sensing, the means for providing including a programmable table circuit storing clock timing as a function of temperature.

2. The timing delay system according to claim 1, wherein said reference parameter is a temperature independent band-gap reference voltage.

3. The timing delay system according to claim 1 wherein said reference parameter is a temperature dependent band-gap reference current.

4. The timing delay system according to claim 1, wherein said second diode has a cross-sectional area which is approximately sixteen times larger than the cross-sectional area of said first diode.

5. The timing delay system according to claim 1, wherein said current output of said first amplifier and said current output of said second amplifier are added and multiplied by a resistor value to obtain a band-gap reference voltage.

6. The timing delay system according to claim 1, wherein said current output of said first amplifier has a positive temperature coefficient and said current output of said second amplifier has a negative temperature coefficient.

7. The timing delay system according to claim 1, wherein said current output of said first amplifier is mirrored and multiplied by a ratio of about Wi/Wo, where Wi corresponds to the width of one of four transistors of said means for sensing said on-chip temperature and Wo corresponds to the width of said at least said first set of transistors.

8. The timing delay system according to claim 1, wherein said reference circuit further comprises a third resistor coupled to at least one of said second set of transistors.

9. The timing delay system according to claim 8, wherein said reference circuit further comprises:

a first by-pass transistor parallel to a first high-resistance resistor in series with said first resistor;

a second by-pass transistor parallel to a second high-resistance resistor in series with said second resistor;

a third by-pass transistor parallel to a third high-resistance resistor in series with said third resistor; and

means for receiving a control signal connected to said first, second and third by-pass transistors, wherein said control signal controls whether said reference circuit by-passes said first, second and third high-resistance resistors to reduce the DC current when said reference circuit is operated during low-power operations.

10. The timing delay system according to claim 8, wherein said first resistor has a resistance value of approximately 10 k-ohms, said second resistor has a resistance value of approximately 83 k-ohms, and said third resistor has a resistance value of approximately 35 k-ohms.

11. The timing delay system according to claim 9, wherein said first high-resistance resistor, said second high-resistance resistor and said third high-resistance resistor have a resistance value of approximately nine times the resistance value of said first resistor, second resistor and said third resistor, respectively.

12. The timing delay system according to claim 1, wherein said means for sensing said on-chip temperature includes a temperature sensing circuit comprising:

a third amplifier having a positive input connected to said first diode and a negative input connected to a fourth resistor, said third amplifier having an output outputting a current output, said output being connected to at least a third set of transistors;

a fifth resistor connected to a first transistor of said at least said third set of transistors;

a sixth resistor connected to a second transistor of said at least said third set of transistors;

a seventh resistor connected to a third transistor of said at least said third set of transistors;

an eight resistor connected to a fourth transistor of said at least said third set of transistors;

a set of amplifiers having a positive input connected to a corresponding one of said fifth, sixth, seventh and eighth resistors and a negative input connected to said reference parameter, each of said set of amplifiers having an output outputting a temperature dependent voltage.

13. The timing delay system according to claim 1, wherein said means for sensing said on-chip temperature includes a temperature sensing circuit comprising:

a third set of transistors having different widths connected to said output of said first amplifier and a corresponding transistor of a fourth set of transistors; and

a transistor being connected to each of said fourth set of transistors and at least one of said second set of transistors, each of said third set of transistors outputting a temperature dependent current.

14. A temperature programmable timing delay system comprising:

means for generating a reference parameter;

means for sensing the on-chip temperature by utilizing at least said reference parameter; and

means for providing a timing adjustment signal for adjusting a clock rate corresponding to an output of said means for sensing. the means for providing including a programmable table circuit storing clock timing as a function of temperature, wherein

the output of said means for sensing is a first binary output and said means for providing comprises means for converting the first binary output to a second binary output,

said means for converting the first binary output to the second binary output being a programmable table circuit, and

said programmable table circuit being selected from the group consisting of mask programmable read-only-memory, flash memory, look-up table, read-only-memory (ROM), field programmable gate array (FPGA), EEPROM, and programmable e-fuse.

15. The timing delay system according to claim 14, wherein said programmable table circuit stores the relationship of the timing delay versus the on-chip temperature.

16. The timing delay system according to claim 14, wherein said means for providing further comprises a temperature dependent timing delay circuit comprising:

an input for receiving said reference parameter and inputs for receiving a respective bit of the second binary output; and

an input for receiving a clock signal and an output for outputting said timing delay signal.

17. The timing delay system according to claim 16, wherein each of said inputs for receiving said respective bit of the second binary output includes a respective diode, and wherein each diode has a respective width different from an adjacent diode for binary weighting said received respective bit.

18. A temperature programmable timing delay system utilizing a band-gap reference and temperature sensor circuit for generating a band-gap reference and sensing the on-chip temperature of an integrated circuit chip. said timing delay system comprising:

a programmable table circuit having inputs for receiving a binary output of said band-gap reference and temperature sensor circuit and outputting a binary output corresponding to the received binary output. the programmable table circuit storing clock timing as a function of temperature; and

a temperature dependent timing delay circuit having inputs for receiving said binary output of said programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of said programmable table circuit, wherein said programmable table circuit is selected from the group consisting of mask programmable read-only-memory, flash memory, look-up table, read-only-memory (ROM), field programmable gate array (FPGA), EEPROM, and programmable e-fuse.

19. The timing delay system according to claim 18, wherein said band-gap reference is a temperature independent band-gap reference voltage having a constant-voltage value.

20. The timing delay system according to claim 18, wherein said band-gap reference is a temperature dependent band-gap reference current having a constant-current value.

21. A method for varying a characteristic of a timing delay signal in accordance with variations of the on-chip temperature of an integrated circuit chip. said method comprising:

generating a reference parameter;

sensing the on-chip temperature of said integrated circuit chip by utilizing at least said reference parameter;

providing the sensed on-chip temperature as a binary reading;

using the binary reading for providing a respective binary code indicating a timing delay using a programmable table circuit storing timing delay as a function of temperature; and

varying the characteristic of the timing delay signal in accordance with the binary code, wherein said step of sensing said on-chip temperature of said integrated circuit chip by utilizing said reference parameter comprises the steps of;

plotting a current versus temperature chart,

plotting a temperature dependent current slope line corresponding to a temperature dependent current slope line measured using a band-gap reference and temperature sensor circuit on said current versus temperature chart, and

plotting a set of temperature dependent current slope lines on said current versus temperature chart, wherein said set of temperature dependent current slope lines correspond to temperature dependent current slope lines measured using said band-gap reference and temperature sensor circuit, wherein the on-chip temperature of said integrated circuit chip is approximately equal to the temperature corresponding to a point where at least one of said set of temperature dependent current slope lines approximately intersects said temperature dependent current slope line.

22. The method according to claim 21, wherein said step of generating said reference parameter comprises the steps of:

generating a first current having a negative temperature coefficient and a second current having a positive temperature coefficient; and

summing portion of said first and second currents and multiplying the sum with a resistance value.

23. The method according to claim 21, wherein said step of sensing said on-chip temperature of said integrated circuit chip by utilizing said reference parameter comprises the steps of:

plotting a voltage versus temperature chart;

plotting a voltage value corresponding to said reference parameter on said voltage versus temperature chart; and

plotting a set of temperature dependent voltage slope lines on said voltage versus temperature chart, wherein said set of temperature dependent voltage slope lines correspond to temperature dependent voltage slope lines measured using a band-gap reference and temperature sensor circuit, wherein the on-chip temperature of said integrated circuit chip is approximately equal to the temperature corresponding to a point where at least one of said set of temperature dependent voltage slope lines approximately intersects said voltage value corresponding to said reference parameter.

24. The method according to claim 21, wherein said reference parameter is a temperature independent band-gap reference voltage having a constant-voltage value.

25. The method according to claim 21, wherein said step of using the binary reading for providing a respective binary code indicating a timing delay comprises the step of inputting the binary reading to a programmable table circuit and outputting the respective binary code, wherein the programmable table circuit stores the relationship of the timing delay versus the on-chip temperature.

26. The method according to claim 25, wherein said programmable table circuit is selected from the group consisting of mask programmable read-only-memory, flash memory, look-up table, read-only-memory (ROM), field programmable gate array (FPGA), EEPROM, and programmable e-fuse.