Method and apparatus for developing and placing a circuit design

• US 6,631,508 B1
• Filed: 06/07/2000
• Issued: 10/07/2003
• Est. Priority Date: 06/07/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Williams, Anthony D.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US09/589,257
• Time in Patent Office: 1,217 Days
• Field of Search: 716/1-14
• US Class Current: 716/121
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method and apparatus for developing placement characteristics of a circuit design in conjunction with developing functional aspects of the circuit. In various embodiments, an application programming interface (API) is programmed in a hardware definition language (HDL). The API provides placement directives that can be called from the HDL code that defines functional characteristics of the circuit. The API can also be used in a testbench in order to analyze both the functional and physical placement characteristics of the design. Since the API is programmed in HDL, the placement generated during the implementation phase is the same as the placement analyzed during functional simulation.

Claims

1. A computer-implemented method for generating a placement for a circuit design, wherein the circuit design is comprised of a logical hierarchy of design objects, comprising:

establishing a physical hierarchy of objects in terms of selected objects from the logical hierarchy in response to directives set forth in a hardware definition language, wherein the physical hierarchy is different from the logical hierarchy;

establishing placement relationships between the objects in the physical hierarchy in response to directives set forth in a hardware definition language; and

generating a placement responsive to the placement relationships established for the physical hierarchy.

2. The method of claim 1, wherein the directives defining the placement relationships include specification of an object above another object in the physical hierarchy, an object below another object in the physical hierarchy, an object to the left of another object in the physical hierarchy, and an object to the right of another object in the physical hierarchy.

3. The method of claim 1, wherein the directives defining the placement relationships include specification of a reflection of an object in the physical hierarchy.

4. A computer-implemented method for generating a placement for a circuit design, wherein the circuit design is comprised of a logical hierarchy of design objects, comprising:

establishing a physical hierarchy of objects in terms of selected objects from the logical hierarchy in response to directives set forth in a hardware definition language, wherein the physical hierarchy is different from the logical hierarchy;

establishing placement relationships between the objects in the physical hierarchy in response to directives set forth in a hardware definition language, including specification of a rotation of an object in the physical hierarchy; and

generating a placement responsive to the placement relationships established for the physical hierarchy.

5. The method of claim 4, wherein the rotation of an object is specified in increments of 90 degrees.

6. In a system including a functional simulator that simulates functionality of a circuit design set forth in hardware description language code in conjunction with a test bench coded in the hardware description language, a computer-implemented method of providing design support, comprising:

generating functional simulation results from the circuit design and test bench;

interpreting directives that define placement characteristics of the circuit design, wherein the directives are set forth in hardware description language code; and

generating, prior to synthesis of the circuit design and in response to the directives, a representation of the placement characteristics that supports graphical depiction of the placement characteristics, whereby functional aspects of the circuit design can be evolved in parallel with placement characteristics.

7. The method of claim 6, wherein the placement characteristics include a floorplan representation.

8. The method of claim 6, wherein the placement characteristics include a representation of a hierarchical relationship between objects in the design.

9. The method of claim 6, wherein the placement characteristics include a floorplan representation and a representation of a hierarchical relationship between objects in the design.

10. The method of claim 6, further comprising generating the placement characteristics in response to directives that define relative positions of objects in the design.

11. The method of claim 6, further comprising generating the placement characteristics in response to directives that translate positional relationships of objects in the design.

12. The method of claim 11, wherein translation of positional relationships includes rotating an object.

13. The method of claim 11, wherein translation of positional relationships includes reflecting an object.

14. The method of claim 6, wherein the representation of the selected placement characteristics is in hypertext markup language.

15. The method of claim 6, wherein the representation of the selected placement characteristics is in Javascript.

16. The method of claim 6, wherein the representation of the selected placement characteristics is in extensible markup language.

17. The method of claim 6, wherein the device is a field programmable gate array.

18. An application programming interface supporting analysis of placement characteristics of a circuit design during logic simulation, comprising:

a first set of procedures callable from code of a hardware definition language, the first set of procedures configured to generate descriptions for placement characteristics for a circuit design specified in the code of the hardware definition language;

a second set of procedures callable from the first set of procedures, the second set of procedures configured to generate placement data suitable for a selected device; and

a third set of procedures callable from code of a hardware definition language, the third set of procedures configured to generate placement characteristics in a format that is viewable via a graphical user interface.

19. The application programming interface of claim 18, wherein the format of the placement characteristics is a markup language.

20. The application programming interface of claim 18, wherein the descriptions of the selected placement characteristics is in Javascript.

21. The application programming interface of claim 18, wherein the device is a field programmable gate array.

22. The application programming interface of claim 18, wherein the placement characteristics include a floorplan representation.

23. The application programming interface of claim 18, wherein the placement characteristics include a representation of a hierarchical relationship between objects in the design.

24. The application programming interface of claim 18, wherein the placement characteristics include a floorplan representation and a representation of a hierarchical relationship between objects in the design.

25. The application programming interface of claim 18, further comprising generating the placement characteristics in response to directives that define relative positions of objects in the design.

26. The application programming interface of claim 18, further comprising generating the placement characteristics in response to directives that translate positional relationships of objects in the design.

27. The application programming interface of claim 26, wherein translation of positional relationships includes rotating an object.

28. The application programming interface of claim 26, wherein translation of positional relationships includes reflecting an object.

29. In a system including a functional simulator that simulates functionality of a circuit design set forth in hardware description language code in conjunction with a test bench coded in the hardware description language, an apparatus for providing design support, comprising:

means for generating functional simulation results from the circuit design and test bench;

means for interpreting directives that define placement characteristics of the design, wherein the directives are set forth in hardware description language code; and

means for generating, prior to synthesis of the circuit design and in response to the directives, a representation of the placement characteristics that supports graphical depiction of the placement characteristics, whereby functional aspects of the circuit design can be evolved in parallel with placement characteristics.