Silicon on insulator device design having improved floating body effect

• US 6,632,686 B1
• Filed: 09/29/2000
• Issued: 10/14/2003
• Est. Priority Date: 09/29/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Narendra, Siva G., Keshavarzi, Ali, Tschanz, James W., De, Vivek K.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Schillinger, Laura M
• Application Number:
  US09/672,696
• Time in Patent Office: 1,110 Days
• Field of Search: 365/156, 365/154, 365/175, 257/295, 257/300, 257/296, 438/3, 438/149, 438/631, 438/14, 438/11, 438/21, 364/491, 364/490, 364/489, 364/488
• US Class Current: 438/14
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be C_dj/(C_dj+C_sj+C_BOX), where C_dj is a capacitance of a drain-body junction, C_sj is a capacitance of a source-body junction and C_BOX is a capacitance of a buried oxide layer.

Claims

1. A method comprising:

determining a capacitance ratio of a design of an integrated circuit, wherein said integrated circuit comprises a substrate, a buried oxide layer formed over said substrate, a source region formed over said buried oxide layer, a drain region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region; and

altering said design of said integrated circuit so as to increase said capacitance ratio of said integrated circuit.

2. The method of claim 1, wherein said capacitance ratio comprises:

3. The method of claim 1, wherein altering said design comprises increasing a thickness of said buried oxide layer.

4. The method of claim 1, wherein altering said design comprises decreasing a dielectric constant of said buried oxide layer.

5. The method of claim 1, wherein altering said design comprises asymmetrically doping said source region and said drain region.

23. The method of claim 1, further comprising forming the integrated circuit having the altered design.

6. A method comprising:

calculating a capacitance ratio of a design for an integrated circuit, wherein said integrated circuit comprises a substrate, a buried layer formed over said substrate, a source region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region;

altering said design so as to increase said capacitance ratio; and

forming said integrated circuit having said altered design.

7. The method of claim 6, wherein said capacitance ratio comprises:

8. The method of claim 7, wherein calculating said capacitance ratio comprises:

determining a capacitance ratio of a first design of said integrated circuit.

9. The method of claim 8, wherein altering said design comprises increasing a thickness of said buried oxide layer.

10. The method of claim 8, wherein altering said design comprises decreasing a dielectric constant of said buried oxide layer.

11. The method of claim 8, wherein altering said design comprises asymmetrically doping said source region and said drain region.

12. A method comprising:

evaluating a first design of an electronic device;

improving said first design of said electronic device so as to increase a capacitance ratio of said electronic device, said capacitance ratio comprising;

13. The method of claim 12, wherein said electronic device comprises a substrate, a buried oxide layer formed over said substrate, a source region formed over said buried oxide layer, and a drain region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region.

14. The method of claim 13, wherein improving said design comprises increasing a thickness of said buried oxide layer.

15. The method of claim 13, wherein improving said design comprises decreasing a dielectric constant of said buried oxide layer.

16. The method of claim 13, wherein improving said design comprises asymmetrically doping said source region and said drain region.

17. A method comprising:

determining a capacitance ratio of a design of an integrated circuit, wherein said integrated circuit comprises a substrate, a buried oxide layer formed over said substrate, a source region formed over said buried oxide layer, a drain region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region;

altering said design of said integrated circuit so as to increase said capacitance of said integrated circuit; and

forming said integrated circuit having said increased capacitance.

18. The method of claim 17, wherein said capacitance ratio comprises:

19. A method of forming an electronic device, said method comprising:

calculating a capacitance ratio of a design for the electronic device, the calculating said capacitance ratio comprises;

determining a capacitance ratio of a first design of said electronic device, and

altering said first design of said electronic device so as to increase said capacitance ratio; and

forming said electronic device having said calculated capacitance ratio.

20. The method of claim 19, wherein altering said design comprises increasing a thickness of a buried oxide layer.

21. The method of claim 19, wherein altering said design comprises decreasing a dielectric constant of a buried oxide layer.

22. The method of claim 19, wherein altering said design comprises asymmetrically doping a source region and a drain region.

24. A method of designing an electronic device comprising:

determining a capacitance ratio of a design of said electronic device, wherein said electronic device comprises a substrate, a buried oxide layer formed over said substrate, a source region formed over said buried oxide layer, a drain region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region; and

altering said design of said electronic device so as to increase said capacitance ratio of said electronic device, the altering comprising increasing a thickness of the buried oxide layer of the electronic device.

25. A method of designing an electronic device comprising:

determining a capacitance ratio of a design of said electronic device, wherein said electronic device comprises a substrate, a buried oxide layer formed over said substrate, a source region formed over said buried oxide layer, a drain region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region; and

altering said design of said electronic device so as to increase said capacitance ratio of said electronic device, the altering comprising decreasing a dielectric constant of the buried oxide layer of the electronic device.

26. A method of designing an electronic device comprising:

determining a capacitance ratio of a design of said electronic device, wherein said electronic device comprises a substrate, a buried oxide layer formed over said substrate, a source region formed over said buried oxide layer, a drain region formed over said buried oxide layer, and a body region formed over said buried oxide layer such that said body region is in between said source region and said drain region; and

altering said design of said electronic device so as to increase said capacitance ratio of said electronic device, the altering comprising asymmetrically doping the source region and the drain region of the electronic device.