Three dimensional structure integrated circuit fabrication process

• US 6,632,706 B1
• Filed: 06/30/2000
• Issued: 10/14/2003
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/607,363
• Time in Patent Office: 1,201 Days
• Field of Search: 438/107, 438/108, 438/109, 438/459, 438/977
• US Class Current: 438/109
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 29/848 by adjacent switching
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A method of forming a stacked integrated circuit, comprising:

forming an integrated circuit on a substrate;

forming a substantially flexible substrate having integrated circuits, including thinning the flexible substrate before dicing the flexible substrate; and

stacking together multiple substantially flexible substrates of integrated circuits on the substrate to form said stacked integrated circuit.

2. The method of claim 1, wherein the thinning of the substrate is done by grinding.

3. The method of claim 2, wherein the thinning of the substrate is done by RIE processing methods.

4. The method of claim 1, wherein the thinning of the substrate is done by RIE processing methods.

5. The method of claim 4, wherein the thinning of the substrate is done by grinding.

6. The method of claim 1, further comprising thinning of the substrate is done by use of a parting layer.

7. The method of claim 1, further comprising forming vertical interconnects between the integrated circuits of the substantially flexible substrate and the integrated circuit formed on the substrate.

8. The method of claim 1, wherein the stacking further comprises forming a non-polymeric bonding layer between at least two of the substantially flexible integrated circuits.

9. The method of claim 8, wherein the non-polymeric bonding layer comprises at least one of a metal and a dielectric material.

10. The method of claim 1, further comprising processing a surface of the thinned flexible substrate by at least one of CVD, RIE, and CMP.

11. The method of claim 1, wherein the thinning of the substantially flexible substrate is done by forming an etch stop.

12. A method of forming a stacked integrated circuit structure, comprising:

bonding together at least two integrated circuit wafers with a non-polymeric layer;

following bonding, processing a surface of one of the integrated circuit wafers to thin said integrated circuit wafer.

13. The method of claim 12, further comprising forming on said surface of said integrated circuit wafer interconnections to integrated circuitry formed on said integrated circuit wafer.

14. The method of claim 13, wherein forming interconnection comprises a metal deposition step.

15. The method of claim 13, wherein forming interconnection comprises thermal diffusion bonding.

16. The method of claim 15, wherein thermal diffusion bonding comprises thermal diffusion bonding of both interconnect metal and field metal.

17. The method of claim 12, further comprising repeating the sequence of bonding and thinning multiple times to form a stacked integrated circuit structure having at least three integrated circuit substrates.

18. The method of claim 12, further comprising the step of forming through said surface of said integrated circuit wafer interconnections to integrated circuitry formed on either of said integrated circuit wafers.

19. The method of claim 12, wherein the thinning of the at least one substantially flexible substrate is done by grinding.

20. The method of claim 12, wherein the thinning of the at least one substantially flexible substrate is done by RIE processing methods.

21. The method of claim 12, wherein the thinning of the at least one substantially flexible substrate is done by forming a parting layer.

22. The method of claim 12, wherein the non-polymeric bonding layer comprises at least one of a metal and a dielectric material.

23. The method of claim 12, further comprising processing a surface of the thinned integrated circuit wafer by at least one of CVD, RIE, and CMP.

24. The method of claim 12, wherein the thinning is done by forming an etch stop.

25. A method of forming a stacked integrated circuit, comprising:

forming an integrated circuit on a first substrate;

forming at least one substantially flexible substrate having integrated circuits, including thinning the at least one flexible substrate before dicing the at least one flexible substrate; and

stacking together the at least one substantially flexible substrate of integrated circuits on the first substrate to form said stacked integrated circuit.

26. The method of claim 25, wherein the thinning of the at least one substantially flexible substrate is done by grinding.

27. The method of claim 26, wherein the thinning of the at least one substantially flexible substrate is done by RIE processing methods.

28. The method of claim 25, wherein the thinning of the at least one substantially flexible substrate is done by RIE processing methods.

29. The method of claim 28, wherein the thinning of the at least one substantially flexible substrate is done by grinding.

30. The method of claim 25, further comprising thinning the at least one substantially flexible substrate is done by use of a parting layer.

31. The method of claim 25, further comprising forming vertical interconnections between the integrated circuits of the at least one substantially flexible substrate and the integrated circuit formed on the first substrate.

32. The method of claim 25, wherein the stacking further comprises forming a non-polymeric bonding layer between at least two of the substantially flexible substrates.

33. The method of claim 25, wherein the non-polymeric bonding layer comprises at least one of a metal and a dielectric material.

34. The method of claim 25, further comprising processing a surface of the thinned flexible substrate by at least one of CVD, RIE, and CMP.

35. The method of claim 25, wherein the thinning is done by forming an etch stop.