Electronic device manufacture

• US 6,632,709 B2
• Filed: 03/29/2001
• Issued: 10/14/2003
• Est. Priority Date: 04/07/2000
• Status: Expired due to Term

• Current Assignee: Innolux Hong Kong Holding Ltd (InnoLux Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Fisher, Carole A., Rohlfing, Frnak W., Young, Nigel D., Brotherton, Stanley D., Ayres, John R. A.
• Primary Examiner(s): Everhart, Caridad
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/821,130
• Publication Number:
  US 20010031519A1
• Time in Patent Office: 929 Days
• Field of Search: 438/149-53, 438/30, 438/48, 438/159-163, 257/24, 257/72, 257/344, 257/336, 257/408
• US Class Current: 438/149
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer (2,46) is etched back underneath a mask layer (20,48). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam (42).

Claims

1. A method of fabricating an electronic device comprising an thin-film transistor, comprising the steps of:

(a) depositing a gate layer over an insulating film, which is over a semiconductor film;

(b) defining a patterned mask layer over the gate layer;

(c) etching to pattern a predetermined distance of the gate layer using the mask layer;

(d) implanting the semiconductor film, using the mask layer and/or the gate layer as an implantation mask to generate a source region and a drain region, and at least a first doped sub-region which is overlapped by the gate layer and an offset sub-region;

(e) over-etching of the gate layer beyond the predetermined distance ranging between about 0.3 um and 3 um to provide an unimplanted gap;

(f) removing the mask layer; and

(g) annealing the semiconductor film with an energy beam.

2. The method of claim 1, further comprising an implantation step after step (f), providing a lower level of doping than step (d).

3. The method of claim 1, wherein step (b) comprises the steps of:

(h) defining a source/drain pattern mask layer;

(i) performing an implantation step which provides a higher level of doping than step (d) to form source and drain regions defined by the source/drain pattern, with areas exposed only to the step (d) implantation forming LDD regions; and

(j) patterning the mask layer to define a gate pattern.

4. The method of claim 1, further comprising, after step (c), the steps of:

(k) defining a source/drain pattern in another mask layer; and

(l) performing an implantation step which provides a higher level of doping than step (d) to form source and drain regions defined by the source/drain pattern, with areas exposed only to the step Cd) implantation forming LDD regions.

5. The method of claim 1, further comprising, prior to step (a), the steps of;

(m) defining an initial patterned mask layer;

(n) performing an implantation step using the initial mask layer of doping than step (d) in regions extending laterally and inwardly beyond the edges of the patterned mask formed in step (b); and

(o) annealing the semiconductor film with an energy beam.

6. The method of claim 5, wherein after the etching back of step (e), the gate layer overlaps a portion of the implanted regions formed in step (n).

7. The method of claim 1, further comprising the step of (p) anodising the gate layer prior to step (e).

8. The method of claim 7, wherein step (d) is carried out before step (p).

9. The method of claim 1, wherein the distance that the gate is etched back in step (e) is 3 μ

m or less.

10. The method of claim 8, wherein the distance that the gate is etched back in step (e) is in the range 0.25 to 0.5 μ

m.

11. The method of claim 1, wherein the gate layer comprises aluminium or a titanium and aluminium dual layer.

12. The method of claim 1, wherein a plurality of the transistors are formed on a substrate as switching elements in a matrix.

20. The method of claim 1, further comprising the step of (p) anodising the gate layer prior to step (f).

13. A method of fabricating an electronic device comprising a thin-film transistor, comprising the steps of;

(a) depositing a gate layer over an insulating film, which is over a semiconductor film;

(b) defining a patterned mask layer over the gate layer;

(c) etching to pattern by a predetermined distance the gate layer using the mask layer;

(d) over-etching back of the gate layer beyond the predetermined distance ranging between about 0.3 um and 3 um to provide an unimplanted gap under the mask layer;

(e) implanting the semiconductor film, using the mask layer and/or the gate layer as an implantation mask to generate a source reunion and a drain region, and at least a first doped sub-region which is overlapped by the gate layer and an offset sub-region;

(f) removing the mask layer; and

(g) annealing the semiconductor film with an energy beam.

14. The method of claim 13, wherein step (c) and step (d) are carried out as a single processing step.

15. The method of claim 13, further comprising an implantation step after step (f), providing a lower level of doping than step (d).

16. The method of claim 13, wherein step (b) comprises the steps of;

(h) defining a source/drain pattern mask layer;

(i) performing an implantation step which provides a higher level of doping than step (d) to form source and drain regions defined by the source/drain pattern, with areas exposed only to the step (d) implantation forming LDD regions; and

(j) patterning the mask layer to define a gate pattern.

17. The method of claim 13, further comprising, after step (d), the steps of:

(k) defining a source/drain pattern in another mask layer; and

(l) performing an implantation step which provides a higher level of doping than step (a) to form source and drain regions defined by the source/drain pattern, with areas exposed only to the step (e) implantation forming LDD regions.

18. The method of claim 13, further comprising, prior to step (a), the steps of:

(m) defining an initial patterned mask layer;

(n) performing an implantation step using the initial mask layer of doping than step (d) in regions extending laterally and inwardly beyond the edges of the patterned mask formed in step (b); and

(o) annealing the semiconductor film with an energy beam.

19. The method of claim 18, wherein after the etching back of step (d), the gate layer overlaps a portion of the implanted regions formed in step (n).