Method of fabricating variable length vertical transistors

• US 6,632,712 B1
• Filed: 10/03/2002
• Issued: 10/14/2003
• Est. Priority Date: 10/03/2002
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Zhou, Mei Sheng, Quek, Elgin, Cha, Randall, Lim, Eng Hua, Zheng, Jia Zhen, Ang, Chew-Hoe, Yen, Daniel
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US10/263,895
• Time in Patent Office: 376 Days
• Field of Search: 438/199, 438/203, 438/206, 438/209, 438/212, 438/213, 438/221, 438/222, 438/223, 438/224, 438/226, 438/227, 438/228, 438/229, 438/230, 438/231, 438/232, 438/267, 438/135, 438/136, 438/137, 438/138, 438/139, 438/156, 438/173, 438/192, 438/154, 438/153, 438/268, 438/269, 438/270, 438/271, 438/279, 438/286, 438/197, 438/585, 257/328, 257/329, 257/330, 257/331, 257/332, 257/369
• US Class Current: 438/212
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

Claims

1. A method of forming vertical, complimentary metal oxide semiconductor (CMOS), devices on a semiconductor substrate, comprising the steps of:

providing a first region of said semiconductor substrate to accommodate first type CMOS devices, and providing a second region of said semiconductor substrate to accommodate second type CMOS devices;

forming a first heavily doped drain region, of a first conductivity type, in a top portion of said first region of said semiconductor substrate, and forming a second heavily doped drain region, of a second conductivity type, in a top portion of said second region of said semiconductor substrate;

depositing a first silicon oxide layer on said semiconductor substrate;

forming a silicon nitride shape on said first silicon oxide layer, in said first region of said semiconductor substrate;

depositing a thin silicon nitride layer and an overlying second silicon oxide layer over said semiconductor substrate;

forming a first channel opening in said second silicon oxide layer, in said thin silicon nitride layer, in said silicon nitride shape, and in said first silicon oxide layer, exposing a portion of a top surface of said first heavily doped drain region, and forming a second channel opening in said second silicon oxide layer, in said thin silicon nitride layer, and in said first silicon oxide layer, exposing a portion of a top surface of said second heavily doped drain region;

forming a first silicon shape in said first channel opening, and forming a second silicon shape in said second channel opening;

depositing a first intrinsic polysilicon layer over said first and second silicon shapes;

performing ion implantation procedures to convert a first portion of said first intrinsic polysilicon layer to a first doped polysilicon region of a first conductivity type, and to convert a second portion of said first intrinsic polysilicon layer to a second doped polysilicon region of a second conductivity type;

depositing a third silicon oxide layer on said first and second doped polysilicon regions;

forming photoresist shapes on said third silicon oxide layer, and on said first and second silicon shapes;

performing an anisotropic dry etching procedure by using photoresist shapes as masks to remove portions of said third silicon oxide layer to form overlying silicon oxide shapes, removing portions of said first and second doped polysilicon regions to form a first polysilicon source shape of a first conductivity type in said first region and a second polysilicon source shape of a second conductivity type in said second region of said semiconductor substrate;

removing portions of said second silicon oxide layer to form underlying silicon oxide spacers;

removing said photoresist shapes;

performing a wet etch procedure to remove said thin silicon nitride layer and said silicon nitride shape, to expose a portion of said first silicon shape, to be used as a first channel region in said first region of semiconductor substrate, and to remove said thin silicon nitride layer to expose a portion of said second silicon shape, to be used as a second channel region in said second region of said semiconductor substrate, wherein said first channel region having a larger channel length than said second channel region;

growing a silicon dioxide gate insulator layer on said first channel region and on said second channel region, while forming a fourth silicon oxide layer on exposed sides of said first and second polysilicon source shapes;

depositing a thick, second intrinsic polysilicon layer on said first silicon oxide layer;

performing ion implantation procedures to convert a first portion of said thick, second intrinsic polysilicon layer to a first doped thick polysilicon region of a first conductivity type, and to convert a second portion of said thick, second intrinsic polysilicon layer to a second doped thick polysilicon region of a second conductivity type; and

performing an anisotropic dry etch procedure by using said silicon oxide shapes as a hard mask to remove portions of said first and second doped thick polysilicon regions, thereby forming a first self-aligned polysilicon gate structure in said first region of said semiconductor substrate, and forming a second self-aligned polysilicon gate structure in said second region of said semiconductor substrate.

2. The method of claim 1, wherein said first type CMOS devices are N channel or NMOS devices, while said second type CMOS devices are P channel or PMOS devices.

3. The method of claim 1, wherein said first heavily doped drain region is a heavily doped N type drain region, obtained via implantation of arsenic or phosphorous ions, at an energy between about 40 to 90 KeV, and at a dose between about 1E15 to 8E15 atoms/cm².

4. The method of claim 1, wherein said second heavily doped drain region is a heavily doped P type drain region, obtained via implantation of boron ions, at an energy between about 2 to 10 KeV, and at a dose between about 1E15 to 6E15 atoms/cm².

5. The method of claim 1, wherein said first silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 200 Angstroms.

6. The method of claim 1, wherein said silicon nitride shape is defined via anisotropic RIE procedures, using Cl₂ as an etchant, performed to a silicon nitride layer which in turn is obtained via LPCVD or PECVD procedures at a thickness between about 300 to 5000 Angstroms.

7. The method of claim 1, wherein said thin silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 500 Angstroms.

8. The method of claim 1, wherein said first channel opening, and said second channel opening, are formed via an anisotropic RIE procedure using CHF₃ as an etchant for said first and second silicon oxide, oxide and using Cl₂ as an etchant for said thin silicon nitride layer and said silicon nitride shape.

9. The method of claim 1, wherein the diameter of said first channel opening, and of said second channel opening, is between about 0.5 to 2.0 um.

10. The method of claim 1, wherein said first silicon shape, and said second silicon shape, are comprised of intrinsic silicon, obtained via selective epitaxial growth of silicon, with the epitaxial silicon growth procedure performed at a temperature between about 800 to 1200°

C., and at a pressure between about 10 to 50 torr.

11. The method of claim 1, wherein said first intrinsic polysilicon layer is obtained via LPCVD procedures, at a thickness between about 400 to 1000 Angstroms.

12. The method of claim 1, wherein said first doped polysilicon region is formed via implantation of arsenic or phosphorous ions into said first portion of said first intrinsic polysilicon layer, at an energy between about 40 to 70 KeV, and at a dose between about 1E15 to 6E15 atoms/cm².

13. The method of claim 1, wherein said second doped polysilicon region is formed via implantation of boron into said second portion of said first intrinsic polysilicon layer, at an energy between about 2 to 10 KeV, and at a dose between about 1E15 to 5E15 atoms/cm².

14. The method of claim 1, wherein said third silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 200 to 500 Angstroms.

15. The method of claim 1, wherein said silicon dioxide gate insulator layer is obtained at a thickness between about 10 to 100 Angstroms, via thermal oxidation procedures performed at a temperature between about 800 to 1200°

C., in an oxygen—

steam ambient.

16. The method of claim 1, wherein said thick, second intrinsic polysilicon layer is obtained via LPCVD procedures, at a thickness between about 1000 to 2000 Angstroms.

17. The method of claim 1, wherein said first doped thick polysilicon region is formed via implantation of arsenic or phosphorous ions into said first portion of said thick, second intrinsic polysilicon layer, performed at an energy between about 50 to 100 KeV, and at a dose between about 1E15 to 6E15 atoms/cm².

18. The method of claim 1, wherein said second doped thick polysilicon region is formed via implantation of boron into said second portion of said thick, second intrinsic, polysilicon layer, performed at an energy between about 20 to 50 KeV, and at a dose between about 1E15 to 5E15 atoms/cm².

19. The method of claim 1, wherein said first and second self-aligned polysilicon gate structures are defined via a selective, anisotropic RIE procedure, using Cl₂ or SF₆ as an etchant.

20. A method of forming vertical CMOS devices, with variable channel lengths, on a semiconductor substrate, comprising the steps of:

providing a first region of said semiconductor substrate to accommodate an N channel (NMOS) device, and providing a second region of said semiconductor substrate to accommodate a P channel (PMOS) device;

forming an N type drain region for said NMOS device, in a top portion of said first region of said semiconductor substrate, and forming a P type drain region for said PMOS device, in a top portion of said second region of said semiconductor substrate;

depositing a first silicon oxide layer on said semiconductor substrate;

depositing a first silicon nitride layer on said first silicon oxide layer;

performing a patterning procedure to remove a portion of said first silicon nitride layer from said first silicon oxide layer in said second region of said semiconductor substrate;

depositing a second silicon nitride layer on said first silicon nitride layer in said first region of said semiconductor substrate, and on said first silicon oxide layer in said second region of said semiconductor substrate;

depositing a second silicon oxide layer on said second silicon nitride layer;

forming an NMOS channel opening in said second silicon oxide layer, in said second silicon nitride layer, in said first silicon nitride layer, and in said first silicon oxide layer, exposing a portion of a top surface of said N type drain region, and forming a PMOS channel opening in said second silicon oxide layer, in said second silicon nitride layer, and in said first silicon oxide layer, exposing a portion of a top surface of said P type drain region;

performing a selective epitaxial deposition of silicon to form a first silicon shape in said NMOS channel opening, and to form a second silicon shape in said PMOS channel opening;

depositing a first intrinsic polysilicon layer on said first and second silicon shapes;

performing ion implantation procedures to convert a first portion of said first intrinsic polysilicon layer, located overlying said first silicon shape, to a first N type polysilicon region, and to convert a second portion of said first intrinsic polysilicon layer, located overlying said second silicon shape, to a first P type polysilicon region;

depositing a third silicon oxide layer on said first N type polysilicon region and said first P type polysilicon region;

forming photoresist shapes on said third silicon oxide layer, and on said first and second silicon shapes performing an anisotropic reactive ion etch (RIE), by using photoresist shapes as masks;

to remove portions of said third silicon oxide layer to form silicon oxide hard mask shapes;

to remove portions of said first N type and first P type polysilicon regions to define an N type polysilicon source shape in said first region of said semiconductor substrate, and to define a P type polysilicon source shape in said second region of said semiconductor substrate; and

to remove portions of said second silicon oxide layer to define silicon oxide spacers removing said photoresist shapes;

performing a wet etch procedure to remove said second silicon nitride layer and said first silicon nitride layer to expose a portion of said first silicon shape to be used as an NMOS channel region in said first region of semiconductor substrate, and exposing a portion of said second silicon shape to be used as a PMOS channel region in said second region of said semiconductor substrate, wherein said NMOS channel region having a larger channel length than said PMOS channel region;

performing a thermal oxidation procedure to grow a silicon dioxide gate insulator layer on said NMOS channel region and on said PMOS channel region, and to grow a silicon oxide layer on exposed sides of said N type polysilicon source shape, and on exposed sides of said P type polysilicon source shape;

depositing a thick, second intrinsic polysilicon layer on said first silicon oxide layer;

performing ion implantation procedures to convert a first portion of said thick, second intrinsic polysilicon layer to a thick N type polysilicon region, and to convert a second portion of said thick, second intrinsic polysilicon layer to a thick P type polysilicon region; and

performing an anisotropic dry etch procedure by using said silicon oxide hard mask shapes as an etch mask to remove portions of said thick N type polysilicon region and to remove portions of said thick P type polysilicon region, thereby forming an N type self-aligned polysilicon gate structure in said first region of said semiconductor substrate, and forming a P type self-aligned polysilicon gate structure in said second region of said semiconductor substrate.

21. The method of claim 20, wherein said first silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 200 Angstroms.

22. The method of claim 20, wherein said first silicon nitride layer is obtained via LPCVD or PECVD procedures at a thickness between about 300 to 5000 Angstroms.

23. The method of claim 20, wherein said second silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 500 Angstroms.

24. The method of claim 20, wherein said NMOS channel opening, and said PMOS channel opening, are formed via an anisotropic RIE procedure, using CHF₃, as an etchant for said first and second silicon oxide layers, and using Cl₂ as an etchant for said first and second silicon nitride layers.

25. The method of claim 20, wherein the diameter of said NMOS channel opening, and the diameter of said PMOS channel opening, is between about 0.5 to 2.0 um.

26. The method of claim 20, wherein said selective epitaxial deposition of silicon is performed at a temperature between about 800 to 1200°

C., and at a pressure between about 10 to 50 torr, using silane or dichlorosilane as a source.

27. The method of claim 20, wherein said first intrinsic polysilicon layer is obtained via LPCVD procedures, at a thickness between about 400 to 1000 Angstroms.

28. The method of claim 20, wherein said third silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 200 to 500 Angstroms.

29. The method of claim 20, wherein said silicon dioxide gate insulator layer is obtained at a thickness between about 10 to 100 Angstroms, via thermal oxidation procedures performed at a temperature between about 800 to 1200°

C., in an oxygen—

steam ambient.

30. The method of claim 20, wherein said thick, second intrinsic polysilicon layer is obtained via LPCVD procedures, at a thickness between about 1000 to 2000 Angstroms.

31. The method of claim 20, wherein said N type self-aligned polysilicon gate structure and said P type self-aligned polysilicon gate structure, are defined via a selective, anisotropic RIE procedure, using Cl₂ or SF₆ as an etchant.