Enhanced grading and sorting of semiconductor devices using modular “plug-in” sort algorithms

• US 6,633,014 B2
• Filed: 02/21/2002
• Issued: 10/14/2003
• Est. Priority Date: 03/30/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Casper, Lance M.
• Primary Examiner(s): Nguyen, Tuan N.
• Application Number:
  US10/080,337
• Publication Number:
  US 20020079252A1
• Time in Patent Office: 600 Days
• Field of Search: 209/571, 209/573, 324/158.1, 324/754, 324/757
• US Class Current: 209/573
• CPC Class Codes: G11C 29/54 Arrangements for designing test circuits, e.g. design for test [DFT] tools
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Claims

1. A test system for qualifying and sorting semiconductor devices comprising:

a semiconductor device tester; and

a test controller operably connected to the semiconductor device tester and programmed with;

a plurality of selected semiconductor device grades;

a downgrade path for each selected semiconductor device grade of said plurality; and

a plurality of sort modules, each sort module being associated with a semiconductor device grade of said plurality and configured to determine if a semiconductor device meets passing criteria for that grade responsive to a test pattern exhibited thereby.

2. The test system of claim 1, wherein the test controller is programmed with a plurality of test registers for provoking a plurality of associated, exhibited test patterns from the semiconductor devices.

3. The test system of claim 1, wherein each of the sort modules of the plurality comprises a self-contained, individually accessible sort module.

4. The test system of claim 1, wherein the plurality of selected semiconductor device grades and the downgrade path are selected at test run time.

5. A test system for qualifying and sorting semiconductor devices comprising:

a semiconductor device tester; and

a test controller operably connected to the semiconductor device tester and programmed with;

a plurality of selected semiconductor device grades;

a downgrade path for each selected semiconductor device grade of said plurality;

a plurality of sort modules, each sort module being associated with a semiconductor device grade of said plurality and configured to determine if a semiconductor device meets criteria for that grade responsive to a test pattern exhibited thereby; and

a plurality of tests wherein at least one test of the plurality is not material to qualification and sorting of the semiconductor devices to at least one grade of the plurality of selected semiconductor device grades, and constrained so as to be applicable only to grades other than the at least one grade.

6. The test system of claim 5, wherein the test controller is programmed with a plurality of test registers for provoking a plurality of associated, exhibited test patterns from the semiconductor devices.

7. The test system of claim 5, wherein each of the sort modules of the plurality comprises a self-contained, individually accessible sort module.

8. The test system of claim 5, wherein the plurality of selected semiconductor device grades and the downgrade path are selected at test run time.

9. The test system of claim 5, wherein the plurality of tests are selected at test run time.