Semiconductor device

• US 6,633,070 B2
• Filed: 09/18/2001
• Issued: 10/14/2003
• Est. Priority Date: 05/01/2001
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Abe, Yuji, Miura, Naruhisa, Oishi, Toshiyuki, Sugihara, Kohei
• Primary Examiner(s): TRAN, THIEN F
• Application Number:
  US09/953,960
• Publication Number:
  US 20020163036A1
• Time in Patent Office: 756 Days
• Field of Search: 257/377, 257/382, 257/384, 257/386, 257/900, 257/19, 257/412, 257/616
• US Class Current: 257/377
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode and the silicon layers and contain respective voids.

Claims

1. A semiconductor device comprising:

a gate electrode on a surface of a semiconductor substrate with a gate insulating film between said gate electrode and said semiconductor substrate, said gate electrode having a wider portion and a narrower portion and including an upper layer of silicon and a lower layer of silicon-germanium, said upper layer including said wider portion and said lower layer including said narrower portion;

sidewall insulating films located on and in contact with opposite side surfaces of said gate electrode; and

source and drain regions in first and second regions of said semiconductor substrate, spaced from each other, with said gate electrode and said sidewall insulating films between said source and drain regions, each of said source and drain regions including a portion at the surface of said semiconductor substrate and a raised portion on a surface of said portion at the surface of said semiconductor substrate, wherein said wider portion of said gate electrode is located closer to said raised portion than said narrower portion of said gate electrode, and said sidewall insulating films are located between and have respective thicknesses between said raised portions and said gate electrode, and include respective voids, lowering capacitance between said gate electrode and said raised portions.

2. The semiconductor device according to claim 1, wherein said raised portion has a height, with respect to the surface of said semiconductor substrate, at least twice the thickness of said sidewall insulating films.

3. The semiconductor device according to claim 1, wherein said wider portion of said gate electrode has a lower end located substantially at a level no higher, with respect to the surface of said semiconductor substrate, than a top surface of said raised portion.

4. A semiconductor device comprising:

a gate electrode on a surface of a semiconductor substrate with a gate insulating film between said gate electrode and said semiconductor substrate;

sidewall insulating films located on and in contact with opposite side surfaces of said gate electrode; and

source and drain regions in first and second regions of said semiconductor substrate, spaced from each other, with said gate electrode and said sidewall insulating films between said source and drain regions, each of said source and drain regions including a portion at the surface of said semiconductor substrate and a raised portion on a surface of said portion at the surface of said semiconductor substrate, wherein said sidewall insulating films are located between and have respective thicknesses between said raised portions and said gate electrode, and include respective voids, lowering capacitance between said gate electrode and said raised portions, said gate electrode extends further from the surface of said semiconductor substrate than said raised portions, and the voids are disposed in portions of said sidewall insulating films no further from the surface of said semiconductor substrate than said raised portions.

5. The semiconductor device according to claim 4, wherein said sidewall insulating films consist of respective single layers.

6. The semiconductor device according to claim 4, wherein said raised portion has a height, with respect to the surface of said semiconductor substrate, at least twice the thickness of said sidewall insulating films.

7. The semiconductor device according to claim 4, wherein said gate electrode has a wider portion and a narrower portion, said wider portion being located closer to said raised portion than said narrower portion.

8. The semiconductor device according to claim 7, wherein the voids are located closer to the surface of said semiconductor substrate than said wider portion of said gate electrode.

9. The semiconductor device according to claim 7, wherein said wider portion has a lower end located at a level equal to or lower than a top surface of said raised portion.

10. The semiconductor device according to claim 7, wherein said wider portion of said gate electrode has a lower end located substantially at a level no higher, with respect to the surface of said semiconductor substrate, than a top surface of said raised portion.