Creating column coherency for burst building in a memory access command stream

• US 6,633,298 B2
• Filed: 07/31/1999
• Issued: 10/14/2003
• Est. Priority Date: 07/31/1999
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ashburn, Jon L, Prouty, Bryan G
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/364,971
• Publication Number:
  US 20030080965A1
• Time in Patent Office: 1,536 Days
• Field of Search: 345/503, 345/533, 345/536, 345/537, 345/531, 345/545, 345/564, 345/570
• US Class Current: 345/537
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A buffer facilitates reordering of memory access commands in a memory access command stream so as to create column coherencies that may be exploited with burst-mode memory cycles. A multi-column data storage buffer is provided. Storage control circuitry stores data associated with a memory access command into the multi-column data storage buffer at a column that corresponds to at least one of the LSBs of the column address associated with the memory access command. Flush control circuitry flushes the data storage buffer, when required, in column order. Each entry in the data storage buffer is associated with a unique valid bit. At flush time, the flush control circuitry analyzes the valid bits to determine an appropriate burst type for executing the memory access commands represented by the flushed buffer contents. The flush control circuitry may indicate the determined burst type to memory controller hardware by means of a burst type flag. The data storage buffer may include multiple lines. Each line is associated with one line in a multi-line column address storage buffer. The storage control circuitry stores at least some of the MSBs of the data column addresses in the column address storage buffer. Column address comparison circuitry determines whether at least some of the MSBs of the column address of an incoming memory access command match those currently stored in a line of the column address storage buffer, and if so, select the matching line, but if not, select an unused line.

Claims

1. A method for creating column coherency in a frame buffer memory access command stream to facilitate burst building of frame buffer memory access commands in a system comprising a frame buffer memory:

providing a multi-column data storage buffer having columns each of which corresponds to at least one the LSBs of a frame buffer column address;

receiving a first frame buffer memory access command accompanied by first frame buffer memory access data and a first frame buffer memory access column address specifying a column in the frame buffer, the first frame buffer memory access column address comprising MSBs and LSBs;

storing the first frame buffer memory access data in the multi-column data storage buffer at a first column that corresponds to the at least one of the LSBs of the frame buffer column which is addressed in the first frame buffer memory access column address;

receiving a second frame buffer memory access command accompanied by second frame buffer memory access data and a second frame buffer memory access column address specifying a column in the frame buffer, the second frame buffer memory access column address comprising MSBs and LSBs;

storing the second frame buffer memory access data in the a multi-column data storage buffer at a second column that corresponds to the at least one of the LSBs of the frame buffer column which is addressed in the second frame buffer memory access column address; and

flushing the first and second frame buffer memory access data from the multi-column data storage buffer in column order.

2. A method according to claim 1, further comprising:

asserting a first valid bit associated with the first column of the multi-column data storage buffer to indicate that frame buffer memory access data is stored therein;

asserting a second valid bit associated with the second column of the multi-column data storage buffer to indicate that frame buffer memory access data is stores therein;

responsive to the first and second valid bits, determining a burst type that would be appropriate when executing the frame buffer memory accesses represented by the first and second frame buffer memory access data; and

accompanying at least one of the first and second frame buffer memory access data at flush time with a flag indicating the determined burst type.

3. A method for creating column coherency in a computer graphics command stream to facilitate burst building of frame buffer commands in a multi-column pixel storage buffer for subsequent delivery to a frame buffer memory:

providing a multi-line, multi-column data storage buffer having columns each of which corresponds to at least one of the LSBs of a frame buffer column address;

receiving a first pixel command from a pipeline, the first pixel command accompanied by first pixel data and a first pixel column address specifying a column in the frame buffer in which the first pixel data is to be stored;

storing the first pixel data in a first line and first column of the multi-line, multi-column pixel storage buffer, wherein the first column of the pixel storage buffer corresponds to the at least one of the LSBs of the frame buffer column which is addressed in the first pixel column address;

storing at least some of the MSBs of the first pixel column address in a column address entry associated with the first line of the pixel storage buffer;

receiving a second pixel command from the pipeline, the second pixel command accompanied by second pixel data and a second pixel column address specifying a column in the frame buffer;

determining whether the MSBs of the second pixel column address match those stored in the column address entry associated with the first line of the pixel storage buffer;

when the MSBs of the second pixel column address match those stored in the column address entry associated with the first line, storing the second pixel data in the first line and second column of the pixel storage buffer, wherein the second column of the pixel storage buffer corresponding to the at least one of the LSBs of the frame buffer column which is addressed in the second pixel column address;

when the MSBs of the second pixel column address do not match those stored in the column address entry associated with the first line, storing the second pixel data in a second line and second column of the pixel storage buffer, wherein the second column of the pixel storage buffer corresponding to the at least one of the LSBS of the frame buffer column which is addressed in the second pixel column address; and

storing at least some of the MSBs of the second pixel column address in a column address entry associated with the second line.

4. A method according to claim 3, further comprising:

asserting valid bits in the first line that are associated with columns of the pixel storage buffer in which pixel data has been stored;

asserting valid bits in the second line that are associated with columns of the pixel storage buffer in which pixel data has been stored;

responsive to the valid bits in the first line, determining a first burst type that would be appropriate when flushing pixel data stored in the first line of the pixel storage buffer;

flushing the pixel data stored in the first line of the pixel storage buffer;

accompanying the flushed pixel data with an indicator of the first burst type;

responsive to the valid bits in the second line, determining a second burst type that would be appropriate when flushing pixel data stored in the second line of the pixel storage buffer; and

flushing the pixel data stored in the second line of the pixel storage buffer; and

accompanying the flushed pixel data with an indicator of the second burst type.

5. A method according to claim 4, wherein the step of flushing the first line further comprises:

flushing invalid pixel data along with the first pixel data as needed to fill a burst; and

accompanying the invalid pixel data so flushed with a flag indicating that it should not be written to the frame buffer memory.

6. Circuitry for creating column coherency in a computer graphics command stream to facilitate burst building of frame buffer memory access commands in a multi-column pixel storage buffer, the circuitry comprising:

a bus for receiving incoming pixel data and pixel column addresses from a pipeline, the pixel column addresses comprising MSBs and LSBs and designating a column in a frame buffer;

a multi-column pixel storage buffer comprising columns each corresponding to at least one LSB of a pixel column address of the frame buffer such that the corresponding LSBs are numerically sequential across sequential columns of the pixel storage buffer;

storage control circuitry for storing received pixel data in the pixel storage buffer at columns of the pixel storage buffer that correspond to the at least one LSB of the pixel column address of the frame buffer column addressed by the pixel column address; and

flush control circuitry for flushing, in column order, the pixel data stored in the multi-column pixel storage buffer.

7. Circuitry according to claim 6, further comprising:

a multi-line column address storage buffer;

wherein the multi-column pixel storage buffer also comprises multiple lines, each line of the pixel storage buffer associated with one line of the column address storage buffer.

8. Circuitry according to claim 7, wherein the storage control circuitry is further operable to store at least some of the MSBs of pixel column address in the column address storage buffer, wherein the circuitry further comprises:

column address comparison and select circuitry for determining whether at least some of the MSBs of the column address of an incoming pixel match those currently stored in a line of the column address storage buffer, and if so, selecting the matching line of the pixel storage buffer, but if not, selecting an unused line of the pixel storage buffer.

9. Circuitry according to claim 8, wherein the bus is also for receiving incoming pixel row/bank addresses, and further comprising:

a row/bank address storage buffer operable to store row/bank addresses; and

circuitry for dynamically allocating lines in the pixel storage buffer and in the column address storage buffer with row/bank addresses stored in the row/bank address storage buffer.

10. Circuitry according to claim 6, where each entry in the pixel storage buffer is associated with a unique valid bit, which is asserted when pixel data is stored in the entry.

11. Circuitry according to claim 10, wherein the flush control circuitry further comprises circuitry for determining, responsive to the valid bits, and appropriate burst mode for flushing the pixel data stored in the pixel storage buffer.

12. Circuitry according to claim 11, further comprising flag generation circuitry for indicating the determined burst type to downstream hardware when the pixel data stored in the pixel storage buffer are flushed.