CMOS image sensor with testing circuit for verifying operation thereof

• US 6,633,335 B1
• Filed: 02/26/1999
• Issued: 10/14/2003
• Est. Priority Date: 02/28/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kwon, Oh Bong, Yang, Woodward, Lee, Suk Joong, Hwang, Gyu Tae
• Primary Examiner(s): Christensen, Andrew
• Assistant Examiner(s): Harris, Tia M.
• Application Number:
  US09/258,448
• Time in Patent Office: 1,691 Days
• Field of Search: 341/120, 341/169, 348/308, 348/302
• US Class Current: 348/308
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: H03M 1/1023 Offset correction H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/1071 Measuring or testing
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp
• CPC Class Codes: H04N 17/002 for television cameras
• CPC Class Codes: H04N 25/69 SSIS comprising testing or correcting structures for circuits other than pixel cells

Abstract

The present invention relates to a picture display using CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a CMOS image sensor having a testing circuit embedded therein and a method for verifying operation of the CMOS image sensor using the testing circuit. The CMOS image sensor according to the present invention includes a control/interface unit for controlling its operation sensor using a state machine and for interfacing the CMOS image sensor with an external system; a pixel array including a plurality of pixels sensing images from an object and generating analogue signals according to an amount of incident light; a converter for converting the analogue signals into digital signals to be processed in a digital logic circuit; and a testing circuit for verifying operations of the converter and the control/interface unit, by controlling the converter.

Claims

1. A CMOS image sensor comprising:

a control/interface means for controlling the CMOS image sensor and outputting test mode information according to a request from a user by using a state machine;

a pixel array including a plurality of pixels sensing images from an object and generating analogue signals according to an amount of incident light;

a conversion means for converting the analogue signals into digital signals to be processed in a digital logic circuit; and

a logic circuit for testing misfunction of the conversion means and the control/interface means, in response to the test mode information.

2. The CMOS image sensor as recited in claim 1, wherein the control/interface means comprises a user invisible register.

3. The CMOS image sensor as recited in claim 2, wherein the control/interface means comprises a plurality of configuration registers which are user visible registers and wherein the configuration registers comprise a test mode register.

4. The CMOS image sensor as recited in claim 3, wherein the conversion means comprises:

a voltage generator for generating first and second reference voltages and for generating a test voltage in response to a control signal from the logic circuit;

a comparison means for comparing the analogue signals with the first reference voltage in a normal mode and for comparing the second reference voltage with the test voltage in a test mode, wherein the normal and test modes are determined by the test mode register of the configuration registers; and

a storage means for storing count signals from the control/interface means in response to outputs from the comparison means.

5. The CMOS image sensor as recited in claim 4, wherein the storage means has a pipelined structure, including first and second buffers, each of which has first and second memory banks, wherein the first memory bank stores offset values generated in the CMOS image sensor and the second memory stores data values from the pixel array.

6. The CMOS image sensor as recited in claim 4, wherein the logic circuit controls the voltage generator for providing the comparison means with the first reference voltage in the normal mode and for providing the comparison means with the test voltage and second reference voltage in the test mode.

7. The CMOS image sensor as recited in claim 4, wherein the test mode register stores first information for testing the misfunction of the state machine of the control/interface means, second information for testing the misfunction of the comparison means and third information for testing the misfunction of the storage means.

8. The CMOS image sensor as recited in claim 4, wherein the count signals are digital signals generated in a code converter.

9. The CMOS image sensor as recited in claim 4, wherein the storage means is asynchronously interfaced with the control/interface means.

10. The CMOS image sensor as recited in claim 5, wherein the storage means comprises a plurality of latch circuits, the latch circuit including:

a first transistor receiving the count signals in response to a control signal from the comparison means;

a second transistor for transferring an output of the first transistor in response to a bank select signal which selects one from the first and second memory banks;

a third transistor for storing the count signals in response to an output of the second transistor; and

a fourth transistor for transferring the data stored in the third transistor to a bit line in response to a column signal from the control/interface means.

11. The CMOS image sensor as recited in claim 6, wherein the CMOS image sensor further comprises a multiplexer for selecting outputs of the storage means in the normal or test mode.

12. The CMOS image sensor as recited in claim 10, wherein the pixel array has N×

M pixels, wherein the comparison means has N operational amplifiers and wherein the storage means has 4×

(the number of bit to be processed)×

N latch circuits.

13. The CMOS image sensor as recited in claim 3, wherein the user invisible register stores contents of the configuration register which is being processed.

14. A CMOS image sensor having a pixel array to output analogue signals sensed from an object, the CMOS image sensor comprising:

an analogue-to-digital converter including;

a) a voltage generator for generating a first reference voltage;

b) a comparison means for comparing the analogue signals with the reference voltage; and

c) a storage means for storing digital signals in response to outputs form the comparison means; and

a logic circuit for detecting whether the analogue-to-digital converter operates erroneously or not, wherein the logic circuit operates in response to test mode information stored in a mode register which the CMOS image sensor has, controls the voltage generator for the comparison means to receive a second reference voltage and a test voltage and stores in the storage means digital signals produced in response to a control signal from the comparison means, and wherein the storage means outputs the stored digital signals to an output terminal of the CMOS image sensor.

15. The CMOS image sensor as recited in claim 14, wherein the CMOS image sensor comprises a user invisible register.

16. The CMOS image sensor as recited in claim 15, wherein the CMOS image sensor comprises a plurality of configuration registers which are user visible registers and wherein the configuration registers comprise a test mode register.

17. The CMOS image sensor as recited in claim 16, wherein the user invisible register stores contents of the configuration register which is being processed.

18. The CMOS image sensor as recited in claim 14, wherein the CMOS image sensor further comprises a multiplexer for selecting outputs of the storage means in a normal or test mode.

19. The CMOS image sensor as recited in claim 14, wherein the storage means has a pipelined structure, the storage means is including first and second buffers, each of which has first and second memory banks, wherein the first memory bank stores offset values generated in the CMOS image sensor and the second memory bank stores data values from the pixel array.

20. The CMOS image sensor as recited in claim 14, wherein the digital signals are count signals produced by a code converter.

21. The CMOS image sensor as recited in claim 19, wherein the storage means comprises a plurality of latch circuits, the latch circuit including:

a first transistor receiving the count signals in response to a control signal from the comparison means;

a second transistor for transferring an output of the first transistor in response to a bank select signal which selects one from the first and second memory banks;

a third transistor for storing the count signals in response to an output of the second transistor; and

a fourth transistor for transferring the data stored in the third transistor to a bit line in response to a column signal.

22. The CMOS image sensor as recited in claim 14, wherein the pixel array has N×

M pixels, wherein the comparison means has N operational amplifiers and wherein the storage means has 4×

(the number of bit to be processed)×

N latch circuits.

23. The CMOS image sensor as recited in claim 14, wherein the storage means is asynchronously interfaced with external circuits outside thereof.