Low voltage charge pump employing distributed charge boosting

• US 6,633,494 B2
• Filed: 10/25/2001
• Issued: 10/14/2003
• Est. Priority Date: 09/14/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mahouti, Kevin Z., Roohparvar, Bob, Rapp, Karl
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US10/004,319
• Publication Number:
  US 20020041503A1
• Time in Patent Office: 719 Days
• Field of Search: 363/60, 363/58, 363/49, 363/50, 363/41, 363/34, 363/61, 363/37, 307/594, 307/450, 307/482, 327/594, 327/458, 327/536, 327/328
• US Class Current: 363/60
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/076 the clock signals being boosted to a value being higher than the input voltage value

Abstract

A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The two-stage charge pump is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages. A high voltage is produced from the two-stage charge pump by alternately adding charge to the power supply voltage in each cycle of the first and second phase clock signals.

Claims

1. A circuit comprising:

a charge pump circuit operable to receive an input voltage and a first clock signal, wherein the charge pump circuit is operable to generate a voltage greater than the input voltage; and

a first pump clock circuit coupled to the charge pump circuit, the first pump clock circuit operable to receive a second clock signal having an amplitude that is approximately equal to an amplitude of the input voltage and the first pump clock circuit operable to increase the amplitude of the second clock signal to an amplitude that is greater than twice an amplitude of the input voltage within an initial single half clock cycle of the second clock signal to generate the first clock signal.

2. The circuit of claim 1 wherein the first clock signal has an amplitude that is approximately an integer multiple of the amplitude of the input voltage.

3. The circuit of claim 1 wherein the input voltage is less than 2 volts.

4. The circuit of claim 1 wherein the input voltage is equal to a supply voltage.

5. A circuit comprising a charge pump circuit coupled to receive an input voltage and coupled to receive a first clock signal having an amplitude that is greater than twice an amplitude of the input voltage, wherein the charge pump circuit uses the first clock signal to generate an output voltage that is greater than the input voltage.

6. The circuit of claim 5 wherein the first clock signal has an amplitude that is approximately an integer multiple of the amplitude of the input voltage.

7. The circuit of claim 5 further comprising a first pump clock circuit coupled to the charge pump circuit, the first pump clock circuit operable to generate the first clock signal.

8. The circuit of claim 5 further comprising a first pump clock circuit operable to receive a second clock signal having an amplitude that is approximately equal to the amplitude of the input voltage and operable to increase the amplitude of the second clock signal to generate the first clock signal.

9. The circuit of claim 5 further comprising a first pump clock circuit having multiple bootstrapping stages, the multiple bootstrapping stages operable to receive a second clock signal having an amplitude that is approximately equal to the amplitude of the input voltage and operable to increase the amplitude of the second clock signal in a half clock cycle of the second clock signal to generate the first clock signal.

10. The circuit of claim 5 wherein the input voltage is less than 2 volts.

11. The circuit of claim 5 wherein the input voltage is equal to a supply voltage.

12. A method comprising:

receiving an input voltage at a charge pump circuit;

receiving a first clock signal at the charge pump circuit, wherein the first clock signal has an amplitude that is greater than twice an amplitude of the input voltage;

generating an output voltage using the first clock signal, wherein the output voltage is greater than the input voltage;

and receiving a second clock signal at a pump clock circuit, the pump clock circuit being operable to increase the amplitude of the second clock signal to an amplitude that is greater than twice an amplitude of the input voltage within an initial single half clock cycle of the second clock signal to generate the first clock signal.

13. The method of claim 12 wherein the input voltage is less than 2 volts.

14. The method of claim 12 wherein the input voltage is equal to a supply voltage.