Low voltage charge pump employing distributed charge boosting
First Claim
1. A circuit comprising:
- a charge pump circuit operable to receive an input voltage and a first clock signal, wherein the charge pump circuit is operable to generate a voltage greater than the input voltage; and
a first pump clock circuit coupled to the charge pump circuit, the first pump clock circuit operable to receive a second clock signal having an amplitude that is approximately equal to an amplitude of the input voltage and the first pump clock circuit operable to increase the amplitude of the second clock signal to an amplitude that is greater than twice an amplitude of the input voltage within an initial single half clock cycle of the second clock signal to generate the first clock signal.
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Accused Products
Abstract
A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The two-stage charge pump is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages. A high voltage is produced from the two-stage charge pump by alternately adding charge to the power supply voltage in each cycle of the first and second phase clock signals.
23 Citations
14 Claims
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1. A circuit comprising:
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a charge pump circuit operable to receive an input voltage and a first clock signal, wherein the charge pump circuit is operable to generate a voltage greater than the input voltage; and
a first pump clock circuit coupled to the charge pump circuit, the first pump clock circuit operable to receive a second clock signal having an amplitude that is approximately equal to an amplitude of the input voltage and the first pump clock circuit operable to increase the amplitude of the second clock signal to an amplitude that is greater than twice an amplitude of the input voltage within an initial single half clock cycle of the second clock signal to generate the first clock signal. - View Dependent Claims (2, 3, 4)
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- 5. A circuit comprising a charge pump circuit coupled to receive an input voltage and coupled to receive a first clock signal having an amplitude that is greater than twice an amplitude of the input voltage, wherein the charge pump circuit uses the first clock signal to generate an output voltage that is greater than the input voltage.
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12. A method comprising:
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receiving an input voltage at a charge pump circuit;
receiving a first clock signal at the charge pump circuit, wherein the first clock signal has an amplitude that is greater than twice an amplitude of the input voltage;
generating an output voltage using the first clock signal, wherein the output voltage is greater than the input voltage;
and receiving a second clock signal at a pump clock circuit, the pump clock circuit being operable to increase the amplitude of the second clock signal to an amplitude that is greater than twice an amplitude of the input voltage within an initial single half clock cycle of the second clock signal to generate the first clock signal. - View Dependent Claims (13, 14)
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Specification