Apparatus and method for synchronizing a clock using a phase-locked loop circuit

• US 6,633,621 B1
• Filed: 03/20/2000
• Issued: 10/14/2003
• Est. Priority Date: 03/20/2000
• Status: Expired due to Fees

• Current Assignee: Torsal Technology Group Limited LLC (Intellectual Ventures LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Geier, George Jeffrey, Hart, Roger Charles, Bishop, Daniel Eric, Schauer, George Arthur, Gross, Joel Lloyd, Moffett, Jeffrey Scott
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US09/531,689
• Time in Patent Office: 1,303 Days
• Field of Search: 375/371, 375/373-376, 375/327, 327/147, 327/150, 327/156, 327/159, 331/11, 331/17, 370/324, 370/516, 370/518
• US Class Current: 375/376
• CPC Class Codes: G04G 7/00 Synchronisation radio-controlled time-pieces G04R
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A system for synchronizing a clock includes a phase-locked loop (PLL) circuit that generates or receives (304) timing errors that are based on timing information from multiple timing sources. Gain blocks (214) weight (306) the timing errors, which are then combined (308) into a loop time error. A loop integrator (226) integrates (310) the loop time error to produce an input used to adjust (312) an oscillator frequency. A corresponding oscillator clock signal is fed back (240) to one or more phase detectors (206), which receive (302) timing reference signals and generate timing errors. When a timing errors indicates that a problem exists with a timing source, the impact of the problematic timing source is reduced (430, 504), or oscillator frequency adjustments are suspended (608). When used on a satellite (700), at least one of the timing errors can be based on times of transmit and times of arrival of time messages exchanged between the satellite and its neighbors (716).

Claims

1. A method for synchronizing a clock using a phase-locked loop circuit which includes an adjustable oscillator and a feedback loop, the method comprising:

receiving multiple timing errors, wherein each timing error is based on timing information from one of multiple timing sources;

combining the multiple timing errors, resulting in a loop time error;

generating an input to the adjustable oscillator based on the loop time error, wherein the adjustable oscillator adjusts an oscillator frequency based on the input, and the oscillator frequency is fed back through the feedback loop, causing the loop time error to approach zero;

monitoring the multiple timing errors;

applying a weighting factor to each of the multiple timing errors, prior to combining the multiple timing errors;

when a particular timing error of the multiple timing errors is out of tolerance, reducing an impact of the particular timing error;

determining whether all of the multiple timing errors are out of tolerance; and

when all of the multiple timing errors are out of tolerance, suspending oscillator frequency adjustments.

2. The method as claimed in claim 1, wherein the phase-locked loop circuit is located on a satellite, and receiving the multiple timing errors comprises receiving a satellite timing error that is related to a time of transmit of a time message from the satellite to another satellite over a cross-link.

3. The method as claimed in claim 2, wherein the satellite timing error is also related to a time of arrival, which is determined by the another satellite and received by the satellite over the cross-link.

4. The method as claimed in claim 1, further comprising;

receiving a timing reference signal from a timing source of the multiple timing sources; and

comparing the timing reference signal to an oscillator clock that is derived from the oscillator frequency, resulting in a timing error of the multiple timing errors.

5. The method as claimed in claim 4, wherein receiving the timing reference signal comprises receiving the timing reference signal from a Global Positioning System receiver.

6. The method as claimed in claim 1, further comprising applying a weighting factor to each of the multiple timing errors, prior to combining the multiple timing errors.

7. The method as claimed in claim 1, further comprising applying a Kalman filter to the multiple timing errors, prior to combining the multiple timing errors.

8. The method as claimed in claim 1, wherein generating the input to the adjustable oscillator comprises integrating the loop time error.

9. The method as claimed in claim 1, wherein combining the multiple timing errors comprises determining an average of the multiple timing errors, and using the average as the loop time error.

10. The method as claimed in claim 1, further comprising generating one or more reference signals from the oscillator frequency.

11. The method as claimed in claim 1, further comprising generating one or more clocks from the oscillator frequency.

12. The method as claimed in claim 11, wherein one of the one or more clocks is an oscillator clock, and the oscillator clock is fed back through the feedback loop and affects the loop time error.

13. The method as claimed in claim 1, further comprising:

determining whether all of the timing errors are out of tolerance; and

when all of the timing errors are out of tolerance, increasing a loop bandwidth by increasing the weighting factors.

14. The method as claimed in claim 1, wherein reducing the impact of the particular timing error comprises reducing the weighting factor applied to the particular timing error.

15. The method as claimed in claim 1, further comprising:

receiving an error message that indicates that a particular timing error is inaccurate; and

reducing an impact of the particular timing error.

16. The method as claimed in claim 15, further comprising:

applying a weighting factor to each of the multiple timing errors, prior to combining the multiple timing errors; and

wherein reducing the impact of the particular timing error comprises reducing the weighting factor applied to the particular timing error.

17. The method as claimed in claim 1, further comprising:

detecting an outage of one of the multiple timing sources;

determining whether all of the multiple timing sources are out; and

when all of the multiple timing sources are out, suspending oscillator frequency adjustments.

18. An apparatus for synchronizing a clock using a phase-locked loop circuit, the apparatus comprising:

at least one phase detector for receiving a timing reference signal from a timing source, and for comparing the timing reference signal to a feedback that is derived from an oscillator frequency, wherein the oscillator frequency is generated by an adjustable oscillator of the phase-locked loop circuit, and wherein comparing the timing reference signal results in a timing error;

a combiner for receiving and combining the timing error and at least one additional timing error, resulting in a combined timing error;

a loop integrator, coupled to the combiner, for generating an input to the adjustable oscillator based on the combined timing error;

the adjustable oscillator, coupled to the loop integrator, for receiving the input and adjusting the oscillator frequency based on the input;

a feedback loop for providing the feedback to the at least one phase detectors; and

wherein the apparatus is located on a satellite, and at least one timing error is derived from a time of transmit and a time of arrival of a time message transmitted by the satellite.

19. The apparatus as claimed in claim 18, further comprising:

multiple gain blocks, coupled to the combiner, for applying weighting factors to the timing error and the at least one additional timing error before they are combined by the combiner.

20. The apparatus as claimed in claim 19, further comprising:

an input controller, coupled to the multiple gain blocks, for adjusting the weighting factors based on the timing error.

21. The apparatus as claimed in claim 18, further comprising;

a clock generator for generating at least one clock based on the oscillator frequency.

22. The apparatus as claimed in claim 18, wherein the timing reference signal is a signal from a Global Positioning System receiver.