Adaptive retry mechanism

• US 6,633,936 B1
• Filed: 09/26/2000
• Issued: 10/14/2003
• Est. Priority Date: 09/26/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hayter, Mark D., Keller, James B., Chui, Kwong-Tak A., Ning, Chun H.
• Primary Examiner(s): Dharia, Rupal
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US09/670,362
• Time in Patent Office: 1,113 Days
• Field of Search: 710/107, 710/110, 710/118, 710/125, 710/306, 710/308
• US Class Current: 710/107
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected.

Claims

1. A method comprising:

establishing a plurality of retry latencies;

determining latencies of transactions on a bus, each latency representing a time period from a first event of a corresponding transaction to a second event of said corresponding transaction; and

selecting a first retry latency for a first transaction from said plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time.

2. The method as recited in claim 1 further comprising:

replacing one of said latencies of said N previous transactions with a first latency of said first transaction; and

selecting a second retry latency of said plurality of retry latencies for a second transaction responsive to said latencies of N previous transactions subsequent to said replacing.

3. The method as recited in claim 2 wherein said one of said latencies of N previous transactions corresponds to a least recent transaction of said previous transactions.

4. The method as recited in claim 1 wherein said plurality of retry latencies includes a minimum retry latency, a maximum retry latency, and a nominal retry latency.

5. The method as recited in claim 4 further comprising initially selecting said nominal retry latency.

6. The method as recited in claim 4 further comprising changing from said nominal retry latency to said minimum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said maximum retry latency.

7. The method as recited in claim 4 further comprising changing from said nominal retry latency to said maximum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said nominal retry latency and less than said maximum retry latency.

8. The method as recited in claim 4 further comprising changing from said maximum retry latency to said minimum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said maximum retry latency.

9. The method as recited in claim 4 further comprising changing from said minimum retry latency to said nominal retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said minimum retry latency and less than said nominal retry latency.

10. The method as recited in claim 1 further comprising retrying said first transaction at said point in time if said second event does not occur before said point in time.

11. The method as recited in claim 1 wherein said first retry latency is a number of clock cycles of a bus clock corresponding to said bus.

12. The method as recited in claim 1 wherein said selecting is performed by a target of said first transaction.

13. The method as recited in claim 12 wherein said determining is performed by said target, and wherein said transactions are transactions targeting said target.

14. The method as recited in claim 1 wherein said first event is a beginning of said corresponding transaction and wherein said second event is a first data transfer of said corresponding transaction.

15. The method as recited in claim 1 wherein said determining comprises measuring said latencies.

16. The method as recited in claim 1 wherein said determining comprises calculating said latencies from multiple internal states of a system including said bus.

17. The method as recited in claim 16 wherein said multiple internal states include a memory read latency, a number of transactions queued in a memory controller, and an amount of traffic on a system bus to which said memory controller is coupled.

18. The method as recited in claim 1 wherein said establishing comprises programming one or more configuration registers with said plurality of retry latencies.

19. The method as recited in claim 1 wherein said establishing comprises fixing said plurality of retry latencies in hardware.

20. A method comprising:

determining latencies of transactions on a bus, each latency representing a time period from a first event of a corresponding transaction to a second event of said corresponding transaction; and

selecting a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time;

wherein said selecting comprises selecting a minimum retry latency of said plurality of retry latencies responsive to at least a first number of said latencies of N previous transactions being latencies greater than a maximum retry latency of said plurality of retry latencies.

21. A method comprising:

determining latencies of transactions on a bus, each latency representing a time period from a first event of a corresponding transaction to a second event of said corresponding transaction; and

selecting a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time;

wherein said selecting comprises selecting a maximum retry latency of said plurality of retry latencies responsive to;

(i) a currently selected retry latency being other than a minimum retry latency of said plurality of retry latencies; and

(ii) at least a first number of said latencies of N previous transactions being latencies less than said maximum retry latency and greater than said currently selected retry latency.

22. A method comprising:

determining latencies of transactions on a bus, each latency representing a time period from a first event of a corresponding transaction to a second event of said corresponding transaction; and

selecting a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time;

wherein said selecting said first retry latency is responsive to;

(i) a currently selected retry latency being a minimum retry latency of said plurality of retry latencies; and

(ii) at least a first number of said latencies of N previous transactions being latencies less than said first retry latency.

23. The method as recited in claim 22 wherein said first retry latency is not a maximum retry latency of said plurality of retry latencies.

24. A method comprising:

determining latencies of transactions on a bus, each latency representing a time period from a first event of a corresponding transaction to a second event of said corresponding transaction; and

selecting a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time;

wherein said first event is a previous data transfer of said corresponding transaction and said second event is a subsequent data transfer of said corresponding transaction.

25. An apparatus comprising:

a buffer configured to store latencies of transactions on a bus, each of said latencies representing a period of time from a first event of a corresponding transaction to a second event of said corresponding transaction; and

a circuit configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions from said buffer, wherein N is a positive integer, and wherein said plurality of retry latencies are established separate from said latencies in said buffer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time.

26. The apparatus as recited in claim 25 wherein said circuit is further configured to replace one of said latencies stored in said buffer with a first latency of said first transaction, and wherein said circuit is further configured to select a second retry latency of said plurality of retry latencies for a second transaction responsive to said latencies of N previous transactions subsequent to said replacing.

27. The apparatus as recited in claim 26 wherein said buffer is a first-in, first-out buffer, and wherein one of said latencies corresponds to a least recent transaction of said previous transactions.

28. The apparatus as recited in claim 25 wherein said plurality of retry latencies includes a minimum retry latency, a maximum retry latency, and a nominal retry latency.

29. The apparatus as recited in claim 28 wherein said circuit is further configured to initially select said nominal retry latency.

30. The apparatus as recited in claim 28 wherein said circuit is further configured to change from said nominal retry latency to said minimum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said maximum retry latency.

31. The apparatus as recited in claim 28 wherein said circuit is further configured to change from said nominal retry latency to said maximum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said nominal retry latency and less than said maximum retry latency.

32. The apparatus as recited in claim 28 wherein said circuit is further configured to change from said maximum retry latency to said minimum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said maximum retry latency.

33. The apparatus as recited in claim 28 wherein said circuit is further configured to change from said minimum retry latency to said nominal retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said minimum retry latency and less than said nominal retry latency.

34. The apparatus as recited in claim 25 further comprising a second circuit coupled to said first circuit, said second circuit configured to retry said first transaction at said point in time if said second event does not occur before said point in time.

35. The apparatus as recited in claim 25 wherein said first retry latency is a number of clock cycles of a bus clock corresponding to said bus.

36. The apparatus as recited in claim 25 wherein said circuit is included in a target of said first transaction.

37. The apparatus as recited in claim 36 wherein said target of said transaction is configured to measure said latencies of said transactions, and wherein said transactions are transactions targeting said target.

38. The apparatus as recited in claim 36 wherein said target of said transaction is configured to calculate said latencies from multiple internal states of a system including said apparatus.

39. The apparatus as recited in claim 38 wherein said multiple internal states include a memory read latency, a number of transactions queued in a memory controller, and an amount of traffic on a system bus to which said memory controller is coupled.

40. The apparatus as recited in claim 25 wherein said first event is a beginning of said corresponding transaction and wherein said second event is a first data transfer of said corresponding transaction.

41. The apparatus as recited in claim 25 further comprising one or more configuration registers programmable with said plurality of retry latencies to establish the plurality of retry latencies separate from said latencies in said buffer.

42. The apparatus as recited in claim 25 wherein said plurality of retry latencies are fixed in hardware.

43. An apparatus comprising:

a buffer configured to store latencies of transactions on a bus, each of said latencies representing a period of time from a first event of a corresponding transaction to a second event of said corresponding transaction; and

a circuit configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time, and wherein said first event is a previous data transfer of said corresponding transaction and said second event is a subsequent data transfer of said corresponding transaction.

44. An apparatus comprising:

a buffer configured to store latencies of transactions on a bus, each of said latencies representing a period of time from a first event of a corresponding transaction to a second event of said corresponding transaction; and

a circuit configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time, and wherein said first retry latency is a minimum retry latency of said plurality of retry latencies responsive to at least a first number of said latencies stored in said buffer being latencies greater than a maximum retry latency of said plurality of retry latencies.

45. An apparatus comprising:

a buffer configured to store latencies of transactions on a bus, each of said latencies representing a period of time from a first event of a corresponding transaction to a second event of said corresponding transaction; and

a circuit configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time, and wherein said first retry latency is a maximum retry latency of said plurality of retry latencies responsive to;

(i) a currently selected retry latency being other than a minimum retry latency of said plurality of retry latencies; and

(ii) at least a first number of said latencies stored in said buffer being latencies less than said maximum retry latency and greater than said currently selected retry latency.

46. An apparatus comprising:

a buffer configured to store latencies of transactions on a bus, each of said latencies representing a period of time from a first event of a corresponding transaction to a second event of said corresponding transaction; and

a circuit configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time, and wherein said circuit is configured to select said first retry latency responsive to;

(i) a currently selected retry latency being a minimum retry latency of said plurality of retry latencies; and

(ii) at least a first number of said latencies stored in said buffer being latencies less than said first retry latency.

47. The apparatus as recited in claim 46 wherein said first retry latency is not a maximum retry latency of said plurality of retry latencies.

48. A carrier medium comprising a database which is operated upon by a program executable on a computer system, the program operating on the database to perform a portion of a process to fabricate an integrated circuit including circuitry described by the database, the circuitry described in the database including:

a buffer configured to store latencies of transactions on a bus, each of said latencies representing a period of time from a first event of a corresponding transaction to a second event of said corresponding transaction; and

a circuit configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions from said buffer, wherein N is a positive integer, and wherein said plurality of retry latencies are established separate from said latencies in said buffer, said first retry latency indicative of a point in time, measured from said first event of said first transaction on said bus, that said first transaction is retried on said bus if said second event of said first transaction does not occur before said point in time.

49. The carrier medium as recited in claim 48 wherein said circuit is further configured to replace one of said latencies stored in said buffer with a first latency of said first transaction, and wherein said circuit is further configured to select a second retry latency of said plurality of retry latencies for a second transaction responsive to said latencies of N previous transactions subsequent to said replacing.

50. The carrier medium as recited in claim 49 wherein said buffer is a first-in, first-out buffer, and wherein one of said latencies corresponds to a least recent transaction of said previous transactions.

51. The carrier medium as recited in claim 48 wherein said first retry latency is a minimum retry latency of said plurality of retry latencies responsive to at least a first number of said latencies stored in said buffer being latencies greater than a maximum retry latency of said plurality of retry latencies.

52. The carrier medium as recited in claim 48 wherein said first retry latency is a maximum retry latency of said plurality of retry latencies responsive to:

(i) a currently selected retry latency being other than a minimum retry latency of said plurality of retry latencies; and

(ii) at least a first number of said latencies stored in said buffer being latencies less than said maximum retry latency and greater than said currently selected retry latency.

53. The carrier medium as recited in claim 48 wherein said circuit is configured to select said first retry latency responsive to:

(i) a currently selected retry latency being a minimum retry latency of said plurality of retry latencies; and

(ii) at least a first number of said latencies stored in said buffer being latencies less than said first retry latency.

54. The carrier medium as recited in claim 53 wherein said first retry latency is not a maximum retry latency of said plurality of retry latencies.

55. The carrier medium as recited in claim 48 wherein said plurality of retry latencies includes a minimum retry latency, a maximum retry latency, and a nominal retry latency.

56. The carrier medium as recited in claim 55 wherein said circuit is further configured to initially select said nominal retry latency.

57. The carrier medium as recited in claim 55 wherein said circuit is further configured to change from said nominal retry latency to said minimum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said maximum retry latency.

58. The carrier medium as recited in claim 55 wherein said circuit is further configured to change from said nominal retry latency to said maximum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said nominal retry latency and less than said maximum retry latency.

59. The carrier medium as recited in claim 55 wherein said circuit is further configured to change from said maximum retry latency to said minimum retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said maximum retry latency.

60. The carrier medium as recited in claim 55 wherein said circuit is further configured to change from said minimum retry latency to said nominal retry latency responsive to at least a first number of said latencies of N previous transactions being latencies greater than said minimum retry latency and less than said nominal retry latency.

61. The carrier medium as recited in claim 48 wherein said circuitry in said database further comprises a second circuit coupled to said first circuit, said second circuit configured to retry said first transaction at said point in time if said second event does not occur before said point in time.

62. The carrier medium as recited in claim 48 wherein said first retry latency is a number of clock cycles of a bus clock corresponding to said bus.

63. The carrier medium as recited in claim 48 wherein said circuit is included in a target of said first transaction.

64. The carrier medium as recited in claim 63 wherein said target of said transaction is configured to measure said latencies of said transactions, and wherein said transactions are transactions targeting said target.

65. The carrier medium as recited in claim 63 wherein said target of said transaction is configured to calculate said latencies from multiple internal states of a system including said apparatus.

66. The carrier medium as recited in claim 65 wherein said multiple internal states include a memory read latency, a number of transactions queued in a memory controller, and an amount of traffic on a system bus to which said memory controller is coupled.

67. The carrier medium as recited in claim 48 wherein said first event is a beginning of said corresponding transaction and wherein said second event is a first data transfer of said corresponding transaction.

68. The carrier medium as recited in claim 48 wherein said first event is a previous data transfer of said corresponding transaction and said second event is a subsequent data transfer of said corresponding transaction.