Distributed real-time operating system providing integrated interrupt management

• US 6,633,942 B1
• Filed: 09/30/1999
• Issued: 10/14/2003
• Est. Priority Date: 08/12/1999
• Status: Expired due to Term

• Current Assignee: Allen-Bradley Company LLC (Rockwell Automation, Inc.)
• Original Assignee: Rockwell Automation Technologies Incorporated (Rockwell Automation, Inc.)
• Inventors: Balasubramanian, Sivaram
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US09/408,670
• Time in Patent Office: 1,475 Days
• Field of Search: 710/260, 710/261, 710/262, 710/263, 710/264, 710/265, 710/266, 710/267, 710/268, 710/269, 709/100, 709/102, 709/103, 709/104, 709/105, 709/107, 709/108, 709/1, 713/502, 713/600, 713/601
• US Class Current: 710/264
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25416 Interrupt
• CPC Class Codes: G05B 2219/31218 Scheduling communication on bus
• CPC Class Codes: G05B 2219/32266 Priority orders
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An interrupt handler is provided for a real-time control system that prevents interrupts which occur asynchronously with respect to control tasks from upsetting guarantees of timely execution of the control tasks. For interrupts associated with the communication of messages between portions of a control task over the distributed system, the interrupts are converted to proxy tasks that may be scheduled like any task in a multitasked-operated system. More generally, interrupts may be assigned to a predetermined interrupt window being a portion of the total processing bandwidth of the processor. In pre-allocating the processor bandwidth to the control tasks, this interrupt window may be subtracted out thereby guaranteeing adequate bandwidth for both interrupt processing and user tasks.

Claims

1. An interrupt manager for use with a processor in a distributed control system, the interrupt manager comprising:

(a) interrupt reception circuitry receiving interrupt signals including a current interrupt;

(b) an interrupt window counter storing an interrupt window indicating time available for processing of interrupts;

(c) a timer refreshing the interrupt window counter at expiration of a window period; and

(e) a masking circuit masking a current interrupt when the interrupt window counter indicates that the processing of the current interrupt would exceed the interrupt window in the current window period.

2. The interrupt manager of claim 1 wherein the interrupt reception circuitry allows masking of interrupts and wherein the interrupt manager upon receiving the interrupt signal masks further interrupts until it is determined that the processing of the current interrupt would not exceed the interrupt window in the current window period.

3. The interrupt manager of claim 1 wherein the interrupt manager provides an estimate of the time needed for processing the current interrupt and uses this estimate to change the value of the interrupt window when the interrupt window indicates that the processing of the current interrupt would not exceed the interrupt window.

4. The interrupt manager of claim 1 wherein the interrupt manager ceases masking the current interrupt upon the resetting of the interrupt window counter by the timer.

5. The interrupt manger of claim 1 including further a resource allocating operating system pre-allocating portions of the window period, excluding the maximum interrupt window to multiple tasks to be executed on the processor so as to guarantee timely execution of those tasks.

6. The interrupt manager of claim 1 wherein the interrupt manager determines whether the processing of the current interrupt would exceed the interrupt window of the current window period by subtracting an estimate of the interrupt processing time from the interrupt window.

7. The interrupt manager of claim 6 wherein the interrupt manager further monitors the execution of the current interrupt and modifies the estimate of the interrupt processing time according the monitoring;

whereby the interrupt processing time is more accurately determined.

8. The interrupt manager of claim 6 wherein upon completion of the current interrupt, the interrupt manager adds the estimate of the interrupt processing time to the interrupt window and subtracts an actual interrupt processing time from the value of the interrupt window;

whereby later estimates of the interrupt window are more accurate.

9. An interrupt manager for use with a processor in a distributed control system, the interrupt manager comprising:

(a) a task scheduler receiving tasks and arranging tasks in a queue according to priorities for execution by the processor;

(b) a communication circuit receiving messages having a priority to generate a communications interrupt; and

(c) an interrupt reception circuit communicating with the task scheduler and the communication circuit to receive communication interrupts and to generate corresponding proxy tasks sent to the task scheduler, the proxy task when executed by the processor causing the communication interrupt to be processed as a task, the proxy tasks having the priority of the message associated with their communication interrupt.

10. The interrupt manager of claim 9 wherein the message priority includes a user assigned priority and a time constraint value and wherein the interrupt reception circuit generates a proxy task having both the user assigned priority and the time constraint value task scheduler.

11. The interrupt manager of claim 10 wherein the task scheduler schedules the task in an order that depends on both the user assigned priority and the time constraint value.