Nonvolatile writeable memory with preemption pin

• US 6,633,950 B1
• Filed: 09/01/2000
• Issued: 10/14/2003
• Est. Priority Date: 09/20/1996
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brown, Charles W., Hazen, Peter K.
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US09/653,768
• Time in Patent Office: 1,138 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/44573 Execute-in-place [XIP]
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it

Abstract

A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.

Claims

1. A nonvolatile memory, comprising:

erase suspend circuitry connected to a memory array;

a preemption pin connected to the erase suspense circuitry; and

a command register connected to the erase suspend circuitry, wherein the erase suspend circuitry suspends an erase cycle of the memory array based on a preemption signal received from the preemption pin or the command register.

2. The nonvolatile memory of claim 1, further comprising erase resume circuitry that resumes the erase cycle based on a resume signal received on the preemption pin.

3. The nonvolatile memory of claim 1, wherein the suspended erase cycle is aborted.

4. The nonvolatile memory of claim 1, further comprising program suspend circuitry, wherein the preemption pin and the control register are connected to the program suspend circuitry which receives the preemption signal from the preemption pin or the command register and suspends a program cycle of the memory array based on the preemption signal.

5. A nonvolatile memory comprising:

a command register that receives a preemption command to preempt an operation being performed by the nonvolatile memory;

a preemption pin that receives a preemption signal to preempt the operation being performed by the nonvolatile memory without using a command so that the operation is suspended; and

a memory control circuitry that preempts the operation being performed by the nonvolatile memory in response to a signal received from either the command register or the preemption pin.

6. The nonvolatile memory of claim 5 wherein the command register further comprises:

a command decoder for decoding the preemption command.

7. The nonvolatile memory of claim 6 wherein the memory control circuitry further comprises:

a suspend circuitry that initiates a suspend operation to suspend the operation being performed by the nonvolatile memory.

8. The nonvolatile memory of claim 7 wherein:

the suspend operation is initiated by the suspend circuitry either by writing a suspend command to the command decoder or by asserting the preemption pin.

9. The nonvolatile memory of claim 8 wherein the memory control circuit further comprises:

a resume circuitry that initiates a resume operation to resume a suspended operation, wherein the resume operation is initiated either by writing a resume command to the command decoder or by asserting the preemption pin.

10. A method of preempting an operation being performed by a nonvolatile memory, comprising:

receiving a preemption signal on a preemption pin or from a command register; and

preempting an operation being performed by the nonvolatile memory in response to the preemption signal received from either the preemption pin, or the command register.

11. The method of claim 10, further comprising resuming the suspended erase cycle.

12. The method of claim 10, wherein the suspended erase cycle is aborted.