Memory card with task registers storing physical addresses

• US 6,633,956 B1
• Filed: 10/18/2000
• Issued: 10/14/2003
• Est. Priority Date: 04/14/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mitani, Hidenori
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/690,730
• Time in Patent Office: 1,091 Days
• Field of Search: 711/115, 711/103, 711/154, 711/163, 711/202, 711/100, 365/185.33, 710/5, 710/4
• US Class Current: 711/115
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory card is provided with flash memories operating in parallel under control of a flash interface. Since these flash memories are allocated for a single task, a RAM is provided with task registers. On request for writing from the host, a controller receives logical addresses and data. The logical addresses are then translated into physical addresses with reference to a management table. The physical addresses for write operation are stored in the task registers. After the status checks on the flash memories are complete, the physical addresses stored in the corresponding task registers are erased.

Claims

1. A memory card, comprising:

a plurality of storage elements; and

a plurality of task registers configured to store physical addresses used in writing to said plurality of storage elements,

wherein one of said physical addresses remains unerased before a status check on corresponding one said plurality of storage elements is OK, and

wherein one of said plurality of task registers alternately stores said physical addresses for at least two of said plurality of storage elements.

2. The memory card according to claim 1, further comprising:

a task register number setting register configured to store a number of said plurality of task registers to be used to alternately store said physical addresses for at least two of said plurality of storage elements, said task register number setting register being located in a RAM attached to a CPU which controls operations of said plurality of storage elements.

3. The memory card according to claim 1, further comprising:

data registers provided in correspondence with said task registers and configured to store write data written at said physical addresses.

4. The memory card according to claim 1, further comprising:

data registers provided in correspondence with said task registers and configured to store write data written at said physical addresses.

5. The memory card according to claim 3, wherein said data registers are located in a buffer for said plurality of storage elements.

6. The memory card according to claim 4, wherein said data registers are located in a buffer for said plurality of storage elements.