Delay/load estimation for use in integrated circuit design

• US 6,634,014 B1
• Filed: 12/12/2000
• Issued: 10/14/2003
• Est. Priority Date: 12/12/2000
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Lindberg, Grant, Graef, Stefan
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US09/735,255
• Time in Patent Office: 1,036 Days
• Field of Search: 716/1-21, 703/14
• US Class Current: 716/104
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.

Claims

1. A method for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said method comprising:

(a) obtaining a description of the IC design in a hardware description language (HDL);

(b) performing floor planning based on the HDL description;

(c) inserting buffers into the IC design based on said floor planning; and

(d) estimating delays in the IC design while taking into account effects of the buffers,

wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.

2. A method according to claim 1, wherein the HDL description comprises a register transfer level (RTL) description.

3. A method according to claim 1, wherein step (b) also includes bus planning and global interconnect planning.

4. A method according to claim 3, further comprising a step (b′

) of estimating delays in the IC design based on said floor planning, bus planning and global interconnect planning, and wherein the buffers are inserted in step (c) based on the delays estimated in said step (b′

).

5. A method according to claim 1, further comprising:

(e) synthesizing the HDL description, without the buffers inserted in step (c) included, to obtain a circuit netlist.

6. A method according to claim 5, further comprising steps of:

(e) performing physical layout based on the circuit netlist; and

(f) inserting buffers into the IC design according to predetermined rules based on said physical layout,

wherein inserting buffers in said step (c) is performed according to rules that are similar to the predetermined rules used in step (f).

7. A method according to claim 1, further comprising a step (b′

) of estimating delays in the IC design based on said floor planning, and wherein the buffers are inserted in step (c) based on the delays estimated in said step (b′

).

8. A method according to claim 1, further comprising a synthesis step of synthesizing the HDL description to produce a structural description of the IC design, wherein said step (c) is performed prior to said synthesis step.

9. A method for performing load estimation prior to physical layout in an integrated circuit (IC) design process, said method comprising:

(a) obtaining a description of the IC design in a hardware description language (HDL);

(b) performing floor planning based on the HDL description;

(c) inserting buffers into the IC design based on said floor planning; and

(d) estimating loads in the IC design while taking into account effects of the buffers,

wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.

10. A method according to claim 9, wherein the HDL description comprises a register transfer level (RTL) description.

11. A method according to claim 9, wherein step (b) also includes bus planning and global interconnect planning.

12. A method according to claim 11, further comprising a step (b′

) of estimating loads in the IC design based on said floor planning, bus planning and global interconnect planning, and wherein the buffers are inserted in step (c) based on the loads estimated in said step (b′

).

13. A method according to claim 9, further comprising:

(e) synthesizing the HDL description, without the buffers inserted in step (c) included, to obtain a circuit netlist.

14. A method according to claim 13, further comprising steps of:

(e) performing physical layout based on the circuit netlist; and

(f) inserting buffers according to predetermined rules based on said physical layout,

wherein inserting buffers into the IC design in said step (c) is performed according to rules that are similar to the predetermined rules used in step (f).

15. A method according to claim 9, further comprising a step (b′

) of estimating loads in the IC design based on said floor planning, and wherein the buffers are inserted in step (c) based on the loads estimated in said step (b′

).

16. A method according to claim 9, further comprising a synthesis step of synthesizing the HDL description to produce a structural description of the IC design, wherein said step (c) is performed prior to said synthesis step.

17. A computer-readable medium storing computer-executable process steps for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said process steps comprising steps to:

(a) obtain a description of the IC design in a hardware description language (HDL);

(b) perform floor planning based on the HDL description;

(c) insert buffers into the IC design based on said floor planning; and

(d) estimate delays in the IC design while taking into account effects of the buffers,

wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.

18. An apparatus for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said apparatus comprising:

(a) means for obtaining a description of the IC design in a hardware description language (HDL);

(b) means for performing floor planning based on the HDL description;

(c) means for inserting buffers into the IC design based on said floor planning; and

(d) means for estimating delays in the IC design while taking into account effects of the buffers,

wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.

19. A computer-readable medium storing computer-executable process steps for performing load estimation prior to physical layout in an integrated circuit (IC) design process, said process steps comprising steps to:

(a) obtain a description of the IC design in a hardware description language (HDL);

(b) perform floor planning based on the HDL description;

(c) insert buffers into the IC design based on said floor planning; and

(d) estimate loads in the IC design while taking into account effects of the buffers,

wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.

20. An apparatus for performing load estimation prior to physical layout in an integrated circuit (IC) design process, said apparatus comprising:

(a) means for obtaining a description of the IC design in a hardware description language (HDL);

(b) means for performing floor planning based on the HDL description;

(c) means for inserting buffers into the IC design based on said floor planning; and

(d) means for estimating loads in the IC design while taking into account effects of the buffers,

wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.