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Delay/load estimation for use in integrated circuit design

  • US 6,634,014 B1
  • Filed: 12/12/2000
  • Issued: 10/14/2003
  • Est. Priority Date: 12/12/2000
  • Status: Expired due to Term
First Claim
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1. A method for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said method comprising:

  • (a) obtaining a description of the IC design in a hardware description language (HDL);

    (b) performing floor planning based on the HDL description;

    (c) inserting buffers into the IC design based on said floor planning; and

    (d) estimating delays in the IC design while taking into account effects of the buffers, wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.

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