Method of fabricating micro-electromechanical switches on CMOS compatible substrates

• US 6,635,506 B2
• Filed: 11/07/2001
• Issued: 10/21/2003
• Est. Priority Date: 11/07/2001
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dalton, Timothy J., Stein, Kenneth J., Petrarca, Kevin S., Volant, Richard P., Groves, Robert A., Cote, Donna R., Subbanna, Seshadri, Bisson, John C.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US10/014,660
• Publication Number:
  US 20030148550A1
• Time in Patent Office: 713 Days
• Field of Search: 438/50, 438/51, 438/52, 438/53, 735/141.6, 735/142.5, 735/041.5, 735/041.4, 738/626.32, 738/626.34, 200/600, 200/181
• US Class Current: 438/52
• CPC Class Codes: B81B 2201/016 having a bridge fixed on two ends and connected to one or more dimples
• CPC Class Codes: B81B 2201/018 Switches not provided for in B81B2201/014 - B81B2201/016
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00611 Processes for the planarisation of structures planarising depositions C23C, H01L
• CPC Class Codes: B81C 2201/0122 Selective addition
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01G 5/40 Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01H 59/0009 making use of micromechanics

Abstract

A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

Claims

1. A method of fabricating a micro-electromechanical (MEM) switch comprising the steps of:

a) depositing a first dielectric layer on a substrate, said first dielectric layer having a plurality of conductive interconnect lines formed therein;

b) depositing a second dielectric layer through which conductive vias are formed, said vias contacting at least one of said plurality of conductive interconnect lines;

c) forming a cavity that is carved out from said second dielectric layer;

d) filling said cavity with sacrificial material and planarizing said sacrificial material; and

e) depositing a third dielectric layer and forming a conductive beam, having said conductive vias contact said conductive beam.

2. The method as recited in claim 1, further comprising the steps of:

f) depositing a fourth dielectric layer and patterning a second cavity conforming to said first cavity;

g) filling said second cavity with sacrificial material and planarizing said sacrificial material

h) depositing a fifth layer to cover said second cavity;

i) patterning and etching a plurality of holes over said sacrificial material; and

j) selectively removing said sacrificial material such that said conductive beam is anchored at at least one end, and leaving the remainder of said conductive beam surrounded by air.

3. The method as recited in claim 2, further comprising the step of adding a sixth dielectric layer to seal said second cavity to protect exposed portions of said conductive beam and to close off released vias in said fifth dielectric layer.

4. The method as recited in claim 3, wherein said protective layer is made of Ta or TaN.

5. The method as recited in claim 1, wherein said step e) is replaced by the step of selectively removing the sacrificial material from said second dielectric layer, said selective removal conforming to the shape of said first cavity.

6. The method as recited in claim 1, wherein said cavity is formed by selectively removing dielectric material from about said conductive beam.

7. The method as recited in claim 1, wherein said step e) is replaced by the step of

e1) patterning the third dielectric layer to selectively free said conductive beam from said third dielectric layer;

and

e2) removing said sacrificial material within said second dielectric layer.

8. The method as recited in claim 1, wherein said conductive interconnect lines are made of copper, and wherein said conductive interconnect lines are inlaid in a dielectric.

9. The method as recited in claim 8, wherein all or portions of said copper interconnect lines are recessed to a degree sufficient to provide a capacitive air gap when said MEM switch is in a closed state.

10. The method as recited in claim 1, wherein said conductive lines are recessed with respect to a top surface of said first dielectric layer to minimize stiction effects.

11. The method as recited in claim 10, further comprising the step of encapsulating said recessed conductive lines.

12. The method as recited in claim 2, wherein said conductive beam is anchored at one or at two of its ends.

13. The method as recited in claim 1, wherein said MEM switch is coupled to a plurality of other metal-dielectric-metal switches that are arranged in a variety of configurations.

14. The method as recited in claim 1, wherein said conductive lines formed in an exposed area of said first cavity act as actuator electrodes for pulling down said conductive beam and provide one or more electrical signal paths.

15. The method as recited in claim 1, wherein said second dielectric layer is deposited to a thickness that is determined by the size of the gap to be formed between said plurality of conductive interconnect lines acting as a lower electrode and said conductive beam.