Wafer-level MEMS packaging

• US 6,635,509 B1
• Filed: 04/12/2002
• Issued: 10/21/2003
• Est. Priority Date: 04/12/2002
• Status: Expired due to Term

• Current Assignee: Teledyne Digital Imaging, Inc. (Teledyne Technologies Incorporated)
• Original Assignee: Dalsa Semiconductor Inc (Teledyne Technologies Incorporated)
• Inventors: Ouellet, Luc
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Owens, Beth E.
• Application Number:
  US10/120,528
• Time in Patent Office: 557 Days
• Field of Search: 438/108, 438/113, 438/33, 438/50, 438/52, 438/53, 438/456, 438/458, 438/106, 438/107
• US Class Current: 438/106
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A competitive, simple, single-substrate wafer-level packaging technique capable of creating a vacuum-sealed protective cavity around moving or other particular components of a MEMS is described. The technique uses common semiconductor materials, processing steps and equipment to provide a stable vacuum environment of, for example less than 1 Pa, in a sealed cavity. The environment protects components of the MEMS against micro-contamination from particles and slurry of a waver dicing process and against fluctuations of atmospheric condition to ensure long term reliability.

Claims

1. A process for fabricating an integrated, wafer-level protective cap on a micro-electronic device comprising:

depositing first and second layers of sacrificial material during a fabrication stage of said device, said first and second layers of sacrificial material being selectively patterned;

depositing and patterning an encapsulation structure over said second layer of sacrificial material;

removing said patterned sacrificial material through the encapsulation structure by a vapor etch to form said micro-electronic device; and

depositing a sealing layer over said encapsulation structure.

2. The method according to claim 1, wherein said first and second layers of sacrificial material have different etch rates.

3. The method according to claim 2, wherein said sealing layer is deposited under vacuum.

4. The method according to claim 3, wherein said vacuum is at least 1 Pa.

5. The method according to claim 1, wherein a titanium-based layer is deposited on said encapsulation structure to form an integrated getter for undesirable gases in said micro-electronic device.

6. The method according to claim 1, wherein said micro-electronic device is a Micro-Electro-Mechanical System (MEMS) device.

7. A process for fabricating an integrated wafer-level protective cap for a micro-Electro-Mechanical-System (MEMS) device comprising:

depositing and patterning a pad oxide layer on a silicon substrate;

depositing and patterning a polysilicon layer on said pad oxide layer and silicon substrates;

depositing and patterning a first layer of a sacrificial material;

depositing and patterning structured In-Situ-Doped-Polysilicon (ISDP) on said first layer of sacrificial materials;

patterning and deep etching said ISDP;

depositing and patterning a second layer of sacrificial material;

depositing an encapsulation structure over said patterned second layer of sacrificial material;

patterning said encapsulation structure;

selectively removing said first and second layers of sacrificial material to create said MEMS; and

depositing, under vacuum, a sealing layer over said encapsulation structure.

8. The method according to claim 7, wherein said first and second layers of sacrificial material are removed by a vapor etch.

9. The method according to claim 8, wherein said first and second layers of sacrificial materials have different etch rates.

10. The method according to claim 9, wherein said sacrificial material is vapor etched using HF vapor.

11. The method according to claim 7, wherein said encapsulation structure has a high Young'"'"'s Modulus.

12. The method according to claim 7, wherein said sealing layer is deposited under a vacuum of at least 1 Pa.

13. The method according to claim 7, wherein a titanium based layer is deposited on said encapsulation structure to act as an integrated getter of gases in said MEMS device.

14. The method according to claim 7, wherein an additional layer is deposited on said sealing layer to enhance rigidity of said sealing layer.

15. The method according to claim 7, wherein said sealing layer is an aluminum alloy which is subjected to an in-situ high temperature self-diffusion to bridge and seal etch pipes in said encapsulation layer.

16. The method according to claim 7, wherein extraneous material is removed to permit contacts to said MEMS.

17. The MEMS fabricated in accordance with the method of claim 16.