Method of fabricating a high-voltage transistor with a multi-layered extended drain structure

• US 6,635,544 B2
• Filed: 09/07/2001
• Issued: 10/21/2003
• Est. Priority Date: 09/07/2001
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Nhu, David
• Application Number:
  US09/948,879
• Publication Number:
  US 20030049930A1
• Time in Patent Office: 774 Days
• Field of Search: 438/197, 438/270, 438/309, 438/316, 438/414, 438/589
• US Class Current: 438/316
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/925 Fluid growth doping control, e.g. delta doping

Abstract

A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer Is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer.

Claims

1. A method for fabricating a high-voltage transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface;

forming source and body regions in the epitaxial layer, the source region being of the first conductivity type and disposed at the top surface of the epitaxial layer, the body region being of a second conductivity type opposite to the first conductivity type;

forming a pair of spaced-apart trenches in the epitaxial layer that define a mesa with first and second sidewall portions;

forming a dielectric layer over each of the first and second sidewall portions;

forming field plate members in the trenches, the field plate members comprising a conductive material that is insulated from the mesa; and

forming an insulated gate member between each of the field plate members and the mesa, a channel being defined adjacent the insulated gate member in the mesa across the body region.

2. The method of claim 1 further comprising:

forming source, gate, and field plate electrodes that connect with the source region, gate members, and field plate members, respectively.

3. The method of claim 1 wherein the first conductivity type is n-type.

4. The method of claim 1 wherein the epitaxial layer is formed with a linearly graded doping profile.

5. The method of claim 1 wherein a doping concentration of the epitaxial layer is lower near the top surface as compared to near the substrate.

6. The method of claim 1 wherein the body region has a thickness in the approximate range of 0.5-3.0 microns.

7. The method of claim 1 wherein the dielectric layer and the field plate members are formed with a reduced spacing between the field plate members and the mesa near the top surface of the epitaxial layer as compared to near the substrate.

8. The method of claim 1 wherein the mesa has a lateral width that is less than 20% of a depth of the trenches.

9. The method of claim 1 wherein the dielectric layer comprises silicon dioxide.

10. The method of claim 1 wherein the dielectric layer has a lateral width that is greater than a lateral width of the mesa.

26. The method of claim 1 wherein the mesa has a lateral width that is less than 20% of a depth of the trenches.

11. A method for fabricating a high-voltage transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type;

etching the epitaxial layer to define a mesa having first and second sidewall portions and a top surface;

forming first and second dielectric layers that cover the first and second sidewall portions, respectively;

forming first and second field plate members of a conductive material respectively insulated from the first and second sidewall portions of the mesa by the first and second dielectric layers;

forming source and body regions in the mesa, the source region being of the first conductivity type and disposed at the top surface of the mesa, the body region being of a second conductivity type opposite to the first conductivity type; and

forming an insulated gate member adjacent the body region.

12. The method of claim 11 wherein the insulated gate is formed in the first and second dielectric layers.

13. The method of claim 11 further comprising:

forming source, gate, and field plate electrodes that connect with the source region, gate member, and field plate members, respectively.

14. The method of claim 11 wherein the first conductivity type is n-type.

15. The method of claim 11 wherein the mesa is formed with a doping concentration that is lower near the top surface as compared to near the substrate.

16. The method of claim 11 wherein the body region has a thickness in the approximate range of 0.5-3.0 microns.

17. The method of claim 11 wherein the dielectric layers are formed with a reduced spacing between the field plate members and the mesa near the top surface of the epitaxial layer as compared to near the substrate.

18. The method of claim 11 wherein the dielectric layers comprises silicon dioxide.

19. The method of claim 11 wherein the dielectric layers each have a lateral width that is greater than a lateral width of the mesa.

20. A method for fabricating a high-voltage transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface;

forming source and body regions in the epitaxial layer, the source region being of the first conductivity type and disposed at the top surface of the epitaxial layer, the body region being of a second conductivity type opposite to the first conductivity type;

forming a pair of spaced-apart trenches in the epitaxial layer that define a mesa with first and second sidewall portions;

forming a dielectric layer over each of the first and second sidewall portions, the dielectric layer having a lateral width that is greater than a lateral width of the mesa;

forming field plate members in the trenches, the field plate members comprising a conductive material that is insulated from the mesa; and

forming an insulated gate member in the dielectric layer between the field plate members and the mesa, a channel region being defined adjacent the insulated gate member in the mesa across the body region;

forming source, gate, and field plate electrodes that connect with the source region, gate members, and field plate members, respectively.

21. The method of claim 20 wherein the first conductivity type is n-type.

22. The method of claim 20 wherein the epitaxial layer is formed with a linearly graded doping profile.

23. The method of claim 20 wherein a doping concentration of the epitaxial layer is lower near the top surface as compared to near the substrate.

24. The method of claim 20 wherein the body region has a thickness in the approximate range of 0.5-3.0 microns.

25. The method of claim 20 wherein the dielectric layer and the field plate members are formed with a reduced spacing between the field plate members and the mesa near the top surface of the epitaxial layer as compared to near the substrate.

27. The method of claim 20 wherein the dielectric layer comprises silicon dioxide.

28. A method for fabricating a high-voltage transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type;

etching the epitaxial layer to define a mesa having first and second sidewall portions and a top surface;

forming first and second dielectric layers that cover the first and second sidewall portions, respectively, the first and second dielectric layers each having a lateral width that is greater than a lateral width of the mesa;

forming first and second field plate members of a conductive material respectively insulated from the first and second sidewall portions of the mesa by the first and second dielectric layers;

forming source and body regions in the mesa, the source region being of the first conductivity type and disposed at the top surface of the mesa, the body region being of a second conductivity type opposite to the first conductivity type; and

forming an insulated gate member laterally adjacent the body region.

29. The method of claim 28 wherein the insulated gate is formed in the first and second dielectric layers.

30. The method of claim 28 further comprising:

forming source, gate, and field plate electrodes that connect with the source region, gate member, and field plate members, respectively.

31. The method of claim 28 wherein the first conductivity type is n-type.

32. The method of claim 28 wherein the mesa is formed with a doping concentration that is lower near the top surface as compared to near the substrate.

33. The method of claim 28 wherein the body region has a thickness in the approximate range of 0.5-3.0 microns.

34. The method of claim 28 wherein the dielectric layers are formed with a reduced spacing between the field plate members and the mesa near the top surface of the mesa as compared to near the substrate.

35. The method of claim 28 wherein the dielectric layers comprise silicon dioxide.

36. A method for fabricating a high-voltage transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type;

etching the epitaxial layer to define a mesa having a width, a height, first and second sidewall portions, and a top surface, the width of the mesa being less than 20% of the height of the mesa;

forming first and second dielectric layers that cover the first and second sidewall portions, respectively;

forming first and second field plate members of a conductive material respectively insulated from the first and second sidewall portions of the mesa by the first and second dielectric layers;

forming source and body regions in the mesa, the source region being of the first conductivity type and disposed at the top surface of the mesa, the body region being of a second conductivity type opposite to the first conductivity type; and

forming an insulated gate member laterally adjacent the body region.

37. The method of claim 36 wherein the insulated gate is formed in the first and second dielectric layers.

38. The method of claim 36 wherein the mesa is formed with a doping concentration that is lower near the top surface as compared to near the substrate.

39. The method of claim 36 wherein the dielectric layers are formed with a reduced spacing between the field plate members and the mesa near the top surface of the mesa as compared to near the substrate.