Method to fabricate poly tip in split gate flash

• US 6,635,922 B1
• Filed: 09/05/2000
• Issued: 10/21/2003
• Est. Priority Date: 04/26/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Jack, Kuo, Di-Son, Hsieh, Chia-Ta, Lin, Yai-Fen, Sung, Hung-Cheng
• Primary Examiner(s): Clark, Sheila V.
• Assistant Examiner(s): RICHARDS, NORMAN DREW
• Application Number:
  US09/654,829
• Time in Patent Office: 1,141 Days
• Field of Search: 257/317, 257/315, 257/321, 257/314
• US Class Current: 257/317
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird'"'"'s beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Claims

1. A split-gate flash memory cell having a sharp poly tip comprising:

a substrate having active and field regions defined;

a floating gate overlying but separated from said substrate by gate oxide;

said floating gate having a top surface with peripheral areas;

said floating gate having inclined sidewalls;

a poly-oxide layer overlying said floating gate forming an interface that is concaved into the top surface of said floating gate, said top surface peripheral areas being inclined;

a poly tip formed at the intersection of the said inclined sidewalls and said inclined top surface peripheral areas of said floating gate; and

a control gate disposed over said floating gate with interpoly oxide therebetween.

2. The split-gate memory cell of claim 1, wherein said floating gate has a thickness between about 800 to 1500 Å

.

3. The split-gate memory cell of claim 1, wherein said control gate a thickness between about 1000 to 3000 Å

.

4. The split-gate memory cell of claim 1, wherein said inclined sidewalls have a slope between about 60 to 80 degrees from the horizontal.