SOI CMOS device with reduced DIBL

• US 6,635,928 B2
• Filed: 08/01/2002
• Issued: 10/21/2003
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra V.
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US10/212,625
• Publication Number:
  US 20020190322A1
• Time in Patent Office: 446 Days
• Field of Search: 438/149, 257/49, 257/347
• US Class Current: 257/347
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Claims

1. A semiconductor transistor device comprising:

a semiconductive substrate;

an insulative layer buried within the semiconductive substrate;

an active layer of semiconductive material above the insulative layer;

a plurality of doped device regions in the active layer;

a gate structure formed on the device regions;

source and drain regions formed in the device regions such that the doping type for the source and drain is complementary to the doping type of the corresponding device region; and

dopant diffusion sources placed within the buried insulator layer underlying the device regions wherein the dopant diffusion sources diffuse into the device regions so as to create a retrograde dopant profile in the device regions.

2. The device of claim 1, wherein the transistor device comprises a field effect transistor.

3. The device of claim 2, wherein the field effect transistor comprises a PMOS device.

4. The device of claim 2, wherein the field effect transistor comprises an NMOS device.

5. The device of claim 2, wherein the field effect transistor comprises a CMOS device.

6. The device of claim 1, wherein the semiconductive substrate comprises a silicon wafer.

7. The device of claim 6, wherein the insulative layer buried within the semiconductive substrate comprises an implanted buried silicon dioxide (BOX) layer.

8. The device of claim 7, wherein the active layer of semiconductive material above the insulative layer comprises a layer of epitaxial silicon.

9. The device of claim 8, wherein the silicon wafer with the BOX layer and the overlying layer of epitaxial silicon comprises a SIMOX wafer.

10. The device of claim 9, wherein the plurality of doped device regions in the active layer are complementarily doped.

11. The device of claim 10, wherein the diffusion of the dopant diffusion source into the device regions so as to create the retrograde dopant profile in the device regions occurs during formation of a passivation layer.

12. The device of claim 11, wherein the retrograde dopant profile has a peak concentration substantially adjacent the interface of the BOX and the active region.

13. The device of claim 12, wherein the retrograde dopant profile in the device region provides the transistor device with improved resistance to drain-induced barrier lowering (DIBL).

14. The device of claim 12, wherein the retrograde dopant profile in the device region provides the transistor device with recombination centers to reduce floating body effects in the transistor device.