Dual probe test structures for semiconductor integrated circuits

• US 6,636,064 B1
• Filed: 08/25/2000
• Issued: 10/21/2003
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Walker, David J., Weiner, Kurt H., Satya, Akella V. S., Adler, David L., Richardson, Neil
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US09/648,092
• Time in Patent Office: 1,152 Days
• Field of Search: 324/754, 324/765, 324/719, 324/158.1, 324/750, 324/751, 324/752, 324/500, 324/501, 324/763, 257/48
• US Class Current: 324/750.3
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.

Claims

1. A semiconductor test structure comprising:

a grounded portion;

a voltage contrast test structure formed over the grounded portion, the voltage contrast test structure having a first portion coupled with the grounded portion and a second portion not coupled with the grounded portion; and

a probe pad coupled to the voltage contrast test structure,

wherein the first portion of the voltage contrast test structure is positioned adjacent to the second portion of the voltage contrast test structure, and

wherein a first subportion of each of the first and second portion is located within a scanning area of a voltage contrast inspection and a second subportion of each of the first and second portion is located outside the scanning area so that a short between the second subportions of the first and second portions of the voltage contrast test structure is detectable during the voltage contrast inspection of the first subportions of the first and second portion.

2. The semiconductor test structure of claim 1, wherein the second portion of the voltage contrast test structure is designed to charge during a voltage contrast inspection to a first voltage potential when the second portion does not have any electrical defects and charge to a second voltage potential when the second portion has an electrical defect so that defects are detectable in the voltage contrast test structure during the voltage contrast inspection.

3. A semiconductor test structure as recited in claim 1, the voltage contrast test structure further comprising:

a lower test structure formed in a lower metal layer of the semiconductor die, the lower conductive test structure having a first end and a second end, wherein the first end is coupled to the grounded portion;

an insulating layer formed over the lower metal layer; and

an upper test structure formed in the upper metal layer of the semiconductor die, the upper conductive test structure being coupled with the second end of the lower conductive test structure, the upper metal layer being formed over the insulating layer,

wherein the probe pad is coupled to the upper test structure.

4. The semiconductor test structure of claim 3, wherein the portion a substrate and the voltage contrast test structure further comprising:

a first via coupled between the first end of the lower test structure and the substrate.

5. The semiconductor test structure of claim 3 wherein the lower test structure is an extended metal line.

6. The semiconductor test structure of claim 1, the voltage contrast test structure further comprising:

a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area of the voltage contrast inspection; and

a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area,

wherein either of the first plurality of test structures or the second plurality of test structures have one or more probe pad(s) coupled to at least one test structure.

7. The semiconductor test structure of claim 6 wherein the first plurality of test structures comprises a plurality of first portions that are coupled to the grounded portion and a plurality of second portions that are not coupled to the grounded portion.

8. The semiconductor test structure of claim 6 wherein the second plurality of test structures comprises a plurality of first portions that are coupled to the grounded portion a plurality of second portions that are not coupled to the grounded portion.

9. The semiconductor test structure of claim 6 wherein the first plurality of test structures comprises a plurality of first portions that are coupled to the grounded portion and a plurality of second portions that are not coupled to the grounded portion and the second plurality of a plurality of first portions that are coupled to the grounded portion and a plurality of second portions that are not coupled to the grounded portion.

10. The semiconductor test structure of claim 6 wherein the second plurality of test structures comprises test structures that are primarily located outside the scanning area.

11. A semiconductor test structure as recited in claim 10 wherein the second plurality of test structures are arranged such that a short associated with a portion of the second plurality of test structures that is located outside the scanning area is detectable by performing voltage contrast on a portion of the second plurality of test structures that is located within the scanning area.

12. The semiconductor test structure of claim 1, wherein the probe pad is coupled to the second portion of the voltage contrast test structure.

13. A semiconductor test structure as recited in claim 12, wherein the first portion of the voltage contrast test structure is formed from a same conductive layer as the second portion of the voltage contrast test structure.

14. A semiconductor test structure as recited in claim 12, wherein the second portion of the voltage contrast test structure is formed from a different conductive layer than the first portion of the voltage contrast test structure.

15. A semiconductor test structure as recited in claim 14, wherein the second portion of the voltage contrast test structure is positioned over the first portion of the voltage contrast test structure.

16. A semiconductor test structure as recited in claim 12, wherein a width of the first subportion of the first portion of the voltage contrast test structure is substantially equal to or less than a width of the second subportion.

17. A semiconductor test structure as recited in claim 12, further comprising a second probe pad coupled to the second portion of the voltage contrast test structure, wherein the first probe pad is coupled to a first end of the second portion of the voltage contrast test structure and the second probe is coupled to a second end of the second portion of the voltage contrast test structure.

18. The semiconductor test structure of claim 1, wherein

the probe pad is coupled with the first portion of the voltage contrast test structure, and

the second subportion of the first portion of the voltage contrast test structure is located outside the scanning area so that an open type defect within the first portion of the voltage contrast test structure is detectable through voltage contrast on the first subportion of the first portion, and

wherein a width of the first subportion is substantially equal to or less than a width of the second subportion.

19. The semiconductor test structure of claim 1, the voltage contrast test structure further comprising:

a lower test structure element;

at least one nonconductive layer over at least a portion of the lower test structure element; and

at least one conductive element within the nonconductive layer,

wherein the probe pad is coupled with the at least one conductive element, and wherein the conductive element is electrically coupled with the lower test structure element.

20. The semiconductor test structure of claim 1, the voltage contrast test structure further comprising:

one or more first conductive test structure(s) that are not coupled with the grounded portion; and

one or more second conductive test structure(s) that are coupled with the grounded portion, the first conductive test structure(s) being interleaved with or adjacent to the second conductive test structure(s),

wherein a first portion of each first test structure is located within the scanning area of the voltage contrast inspection and a second portion of each first test structure is located outside the scanning area so that a short between any second portion of each first test structure and an adjacent second test structure is detectable through voltage contrast on any first portion of each first test structure, and

wherein the first probe pad is coupled to a first end of a selected one of the first test structure(s);

a second probe pad coupled to a second end of the selected first test structure;

a third probe pad coupled to the first end of the selected first test structure; and

a fourth probe pad coupled to the second end of the selected first test structure.

21. A semiconductor wafer comprising a plurality of semiconductor test structures as recited in claim 1.

22. A semiconductor test structure as recited in claim 20, wherein the second conductive test structures are coupled together at a first end that is opposite a second end, the first end being coupled to the grounded portion.