Upscaled clock feeds memory to make parallel waves

• US 6,636,096 B2
• Filed: 10/03/2001
• Issued: 10/21/2003
• Est. Priority Date: 10/06/2000
• Status: Expired due to Term

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Thommen, Daniel, Schaffer, Bernhard, Drenth, Joannes Christianus
• Primary Examiner(s): Lam, Tuan T.
• Application Number:
  US09/969,715
• Publication Number:
  US 20020052071A1
• Time in Patent Office: 748 Days
• Field of Search: 327/291, 327/295, 327/296, 327/297, 327/298, 327/141, 327/144
• US Class Current: 327/295
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An integrated circuit has a clock input for receiving a primary clock signal, clock reconfiguring device fed by the clock input for generating one or more secondary reconfigured clock signals, and utility circuitry fed by the clock reconfiguring device for constituting application utility functions under synchronization by the secondary clock signals. In particular, the clock input a clock upscaling device for from the primary clock signal generating an intermediate clock signal with an upscaled frequency for thereby feeding the clock reconfiguring device. Furthermore, the clock reconfiguring device a has late-programmable and low power memory driven by the intermediate clock signal for generating the secondary reconfigured clock signals. These are wave-shape patterns read-out from a plurality of separately and sequentially drivable memory locations.

Claims

1. An integrated circuit comprising clock input means for receiving a primary clock signal, clock reconfiguring means fed by said clock input means for generating one or more secondary reconfigured clock signals, and utility circuitry fed by said clock reconfiguring means for constituting application utility functions under synchronization by said secondary clock signals,

being characterized in that said clock input means comprise clock upscaling means for from said primary clock signal generating an intermediate clock signal with an upscaled frequency for thereby feeding said clock reconfiguring means,

said clock reconfiguring means comprising late-programmable and low power memory means driven by said intermediate clock signal for generating said secondary reconfigured clock signals as wave-shape patterns read-out from a plurality of separately and sequentially drivable memory locations.

2. An integrated circuit as claimed in claim 1, wherein said clock upscaling means are PLL-based.

3. An integrated circuit as claimed in claim 1, wherein said late-programmable memory means are ROM-based.

4. An integrated circuit as claimed in claim 1, wherein said late-programmable memory means are RAM-based.

5. An integrated circuit as claimed in claim 1, wherein said late-programmable memory means are arranged to feed demultiplexer means (70) under control of an associated control signalization (72) for selectively and statically transferring only a subset of all wave-shape patterns stored for synchronizing said application utility functions.

6. An integrated circuit as claimed in claim 1, wherein said application utility is mobile telecom.

7. An integrated circuit as claimed in claim 1, wherein said wave-shape patterns define various duty cycle values and/or non-standard wave shapes.

8. An integrated circuit as claimed in claim 1, wherein said application utility functions represent diverse clock domains on a single integrated substrate.