Structure to reduce the degradation of the Q value of an inductor caused by via resistance
First Claim
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1. A method of creating a spiral inductor, comprising the steps of:
- providing a substrate, interconnect lines having been provided over said substrate for connection thereto of inductor terminals;
depositing a layer of dielectric over said substrate, thereby including said interconnect lines;
depositing a layer of passivation over said layer of dielectric;
patterning said layer of dielectric and said layer of passivation, creating first via openings through said layers of dielectric and passivation aligned with said interconnect lines, exposing the surface of said interconnect lines;
depositing a first layer of metal over said layer of passivation, including inside surfaces of said first via openings, said first layer of metal being deposited to a thickness between about 6 and 26 μ
m;
patterning and etching said deposited first layer of metal, creating metal lines for an inductor, further creating first vias for interconnecting said inductor to said exposed surfaces of said interconnect lines, said first vias being connected to said inductor and forming terminal ports for said inductor, said first vias having a surface area overlying said layer of passivation larger than about 0.17×
0.17 μ
m; and
depositing a layer of polyimide over said layer of passivation, including said created inductor and inside surfaces of said created first vias.
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Abstract
A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias. The invention can further be extended by creating at least one second via through the thick layer of polyimide aligned with at least one of the created first vias. A patterned and etched layer of metal that fills the second via creates a re-distribution layer on the surface of the thick layer of polyimide for flip chip interconnects.
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Citations
22 Claims
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1. A method of creating a spiral inductor, comprising the steps of:
-
providing a substrate, interconnect lines having been provided over said substrate for connection thereto of inductor terminals;
depositing a layer of dielectric over said substrate, thereby including said interconnect lines;
depositing a layer of passivation over said layer of dielectric;
patterning said layer of dielectric and said layer of passivation, creating first via openings through said layers of dielectric and passivation aligned with said interconnect lines, exposing the surface of said interconnect lines;
depositing a first layer of metal over said layer of passivation, including inside surfaces of said first via openings, said first layer of metal being deposited to a thickness between about 6 and 26 μ
m;
patterning and etching said deposited first layer of metal, creating metal lines for an inductor, further creating first vias for interconnecting said inductor to said exposed surfaces of said interconnect lines, said first vias being connected to said inductor and forming terminal ports for said inductor, said first vias having a surface area overlying said layer of passivation larger than about 0.17×
0.17 μ
m; and
depositing a layer of polyimide over said layer of passivation, including said created inductor and inside surfaces of said created first vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
creating at least one opening through said layer of polyimide, said at least one opening being aligned with at least one of said first vias;
depositing a second layer of metal over said layer of polyimide, including inside surfaces of said at least one opening created through said layer of polyimide, said second layer of metal being deposited to a thickness between about 6 and 26 μ
m; and
patterning said second layer of metal, creating at least one second via being aligned with at least one of said first vias, providing a re-distribution layer on said layer of polyimide for flip chip interconnects.
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8. The method of claim 7 wherein said second via has a surface area overlying said layer of polyimide of about 7×
- 7 μ
m.
- 7 μ
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9. The method of claim 7 wherein said second via has a surface area overlying said layer of polyimide larger than about 7×
- 7 μ
m.
- 7 μ
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10. The method of claim 7 wherein said second layer of metal is deposited using plating or screen printing techniques.
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11. The method of claim 7 wherein said second layer of metal is gold, copper or platinum.
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12. The method of claim 7 wherein said second via has a surface area overlying said layer of polyimide larger than about 0.17×
- 0.17 μ
m.
- 0.17 μ
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13. The structure of a spiral inductor, comprising:
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a substrate, interconnect lines over said substrate for connection thereto of inductor terminals;
a layer of dielectric over said substrate, thereby including said interconnect lines;
a layer of passivation over said layer of dielectric;
first via openings through said layers of dielectric and passivation aligned with said interconnect lines, exposing said interconnect lines, said first via openings being large enough for deposition of a layer of metal with a thickness between about 6 and 26 μ
m over inside surfaces of said first vias;
a first layer of metal over said layer of passivation, including inside surfaces of said first via openings created through said layers of passivation and dielectric, said first layer of metal having a thickness between about 6 and 26 μ
m;
said deposited first layer of metal having been patterned and etched, creating metal lines for an inductor, further creating first vias for interconnect said inductor to said exposed surfaces of said interconnect lines, said first vias being connected to said inductor and forming terminal ports for said inductor, said first vias having a surface area overlying said layer of passivation larger than about 0.17×
0.17 μ
m; and
a layer of polyimide deposited over said layer of passivation, including said created inductor and inside surfaces of said created first vias. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
at least one opening created through said layer of polyimide, said at least one opening being aligned with at least one of said first vias;
a second layer of metal deposited over said layer of polyimide, including inside surfaces of said at least one opening created through said layer of polyimide, said second layer of metal being deposited to a thickness between about 6 and 26 μ
m; and
at least one second via created through said layer of polyimide aligned with at least one of said first vias, providing a re-distribution layer on said layer of polyimide for flip chip interconnects.
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19. The structure of claim 18, said at least one second via having a surface area overlying said layer of polyimide of about 7×
- 7 μ
m.
- 7 μ
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20. The structure of claim 18, said at least one second via having a surface area overlying said layer of polyimide larger than about 7×
- 7 μ
m.
- 7 μ
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21. The structure of claim 18, wherein said second layer of metal is gold, copper or platinum.
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22. The structure of claim 18, said at least one second via having a surface area overlying said layer of polyimide larger than about 0.17×
- 0.17 μ
m.
- 0.17 μ
Specification
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsWong, Shyh-Chyi, Tsai, Chaochieh
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Primary Examiner(s)MAI, ANH T
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Application NumberUS09/950,224Publication NumberTime in Patent Office771 DaysField of Search336/200, 336/223, 336/232, 257/774, 257/758, 438/637, 438/618US Class Current336/200CPC Class CodesH01F 17/0006 Printed inductances printed...H01F 41/041 Printed circuit coils appar...H01L 27/08 including only semiconducto...
