Video and graphics system with an MPEG video decoder for concurrent multi-row decoding

• US 6,636,222 B1
• Filed: 08/18/2000
• Issued: 10/21/2003
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bhatia, Sandeep, Valmiki, Ramanujan K.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Sajous, Wesner
• Application Number:
  US09/641,936
• Time in Patent Office: 1,159 Days
• Field of Search: 345/597, 345/601, 345/602, 345/604, 345/501, 345/502-503, 345/505-506, 345/519-522, 345/530-532, 345/545-549, 345/555-556, 345/564-567, 345/536-538, 348/589, 348/599, 348/669, 348/597, 348/571, 348/715, 348/461, 348/510, 348/721, 348/708, 348/705, 348/697, 348/554, 348/565, 710/124, 710/316, 710/7, 710/265, 710/20, 375/240, 375/253, 375/240.25, 375/240.13, 375/240.16, 375/240.29, 375/262, 375/265, 375/246, 382/232-236
• US Class Current: 345/505
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 2340/06 Colour space transformation
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/00 : Television systems details H04N3/00, H04N5/00; methods or arrangements, for coding, decoding, compressing or decompressing digital video signals H04N19/00; selective content distribution H04N21/00
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers
• CPC Class Codes: Y10S 502/506 : Method of making inorganic composition utilizing organic compound, except formic, acetic, or oxalic acid or salt thereof

Abstract

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Claims

1. A video decoding system for decoding video data, said system comprising:

at least one decode path for decoding the video data, said at least one decode path comprising a first processing element and a second processing element,

wherein the video data is organized into a plurality of rows, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion, and said at least one decode path concurrently decodes at least two rows of the video data,

wherein the first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock, and

wherein the first portion comprises a macroblock header and the second portion comprises block layer data.

2. The video decoding system of claim 1 wherein said at least one decode path is implemented on an integrated circuit chip.

3. The video decoding system of claim 1 wherein the video data comprises MPEG-2 video data and each row comprises at least one SLICE comprising the macroblocks.

4. The video decoding system of claim 3 wherein the first processing element decodes the first portion of a first macroblock while the second processing element concurrently decodes the second portion of a second macroblock.

5. The video decoding system of claim 4 wherein the first macroblock is from a first SLICE and the second macroblock is from a second SLICE.

6. The video decoding system of claim 1 wherein at least one of the first and second processing elements comprises a variable length decoder.

7. The Video decoding system of claim 1 further comprising a video decoding engine for reading the video data from memory and providing the video data to said at least one decode path.

8. The video decoding system of claim 1 wherein the video data comprises at least one HDTV video data.

9. A video decoding system for decoding video data, said system comprising:

at least one decode path for decoding the video data, said at least one decode path comprising a first processing element and a second processing element,

wherein the video data is organized into a plurality of rows, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion, and said at least one decode path concurrently decodes at least two rows of the video data, and

wherein the first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock, the system

further comprising a switch wherein the first processing element decodes the first portion of a first macroblock and the switch provides the second portion of the first macroblock to the second processing element for decoding.

10. The video decoding system of claim 9 wherein the first processing element decodes the first portion of a second macroblock while the second processing element concurrently decodes the second portion of the first macroblock.

11. A video decoding system for decoding video data, said system comprising:

at least one decode path for decoding the video data, said at least one decode path comprising a first processing element and a second processing element,

wherein the video data is organized into a plurality of rows, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion, and said at least one decode path concurrently decodes at least two rows of the video data,

wherein the first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock,

wherein the video data comprises MPEG-2 video data and each row comprises at least one SLICE comprising the macroblocks, and wherein said at least one decode path comprises first and second decode paths, wherein the first decode path comprises the first processing element and the second processing element for concurrently decoding the macroblocks of first and second SLICEs, and the second decode path comprises a third processing element and a fourth processing element for concurrently decoding the macroblocks of third and fourth SLICEs, and wherein the first and second SLICEs are decoded in parallel with the third and fourth SLICEs.

12. A method of decoding video data comprising the steps of:

receiving a plurality of rows of the video data, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion; and

concurrently decoding at least two rows of the video data,

wherein a first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock, and

wherein the first portion comprises a macroblock header and the second portion comprises block layer data.

13. The method of decoding video data of claim 12 wherein the video data comprises MPEG-2 video data and each row comprises at least one SLICE comprising the macroblocks.

14. The method of decoding video data of claim 13 wherein the step of concurrently decoding at least two rows of the video data comprises the step of decoding the second portion of a first macroblock while concurrently decoding the first portion of a second macroblock.

15. The method of decoding video data of claim 13 wherein the step of concurrently decoding at least two rows of the video data comprises the steps of decoding a first portion of a first macroblock using the first processing element and providing a second portion of the first macroblock to the second processing element for decoding.

16. The method of decoding video data of claim 12 wherein the step of concurrently decoding at least two rows of the video data comprises the step of variable length decoding.

17. The method of decoding video data of claim 12 wherein the step of receiving a plurality of rows of the video data comprises the step of reading the plurality of rows of video data from memory.

18. The method of decoding video data of claim 12 wherein the step of receiving a plurality of rows of the video data comprises the step of receiving at least one HDTV video data.

19. A method of decoding video data comprising the steps of:

receiving a plurality of rows of the video data, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion; and

concurrently decoding at least two rows of the video data,

wherein a first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock,

wherein the video data comprises MPEG-2 video data and each row comprises at least one SLICE comprising the macroblocks,

wherein the step of concurrently decoding at least two rows of the video data comprises the steps of decoding a first portion of a first macroblock using the first processing element and providing a second portion of the first macroblock to the second processing element for decoding, and

wherein the step of concurrently decoding at least two rows of the video data further comprises the steps of decoding the first portion of a second macroblock using the first processing element while concurrently decoding the second portion of the first macroblock using the second processing element.

20. The method of decoding video data of claim 19 wherein the first macroblock is from a first SLICE while the second macroblock is from a second SLICE.

21. The video decoding system of claim 20, wherein the first and second SLICEs are from different rows.

22. A method of decoding video data comprising the steps of:

receiving a plurality of rows of the video data, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion; and

concurrently decoding at least two rows of the video data,

wherein a first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock,

wherein the video data comprises MPEG-2 video data and each row comprises at least one SLICE comprising the macroblocks, and

wherein the step of concurrently decoding at least two rows of the video data comprises the steps of concurrently decoding the macroblocks of first and second SLICEs, and concurrently decoding the macroblocks of third and fourth SLICEs, wherein the first and second SLICES are decoded in parallel with the third and fourth SLICEs.

23. A video and graphics system comprising:

a transport processor for receiving one or more compressed data streams and for extracting video data;

a video decoder including at least one decode path for decoding the video data to generate decoded video data, said at least one decode path comprising a first processing element and a second processing element; and

a video compositor for blending the decoded video data with graphics,

wherein the video data is organized into a plurality of rows, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion, and said at least one decode path concurrently decodes at least two rows of the video data,

wherein the first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock, and

wherein the first portion comprises a macroblock header and the second portion comprises block layer data.

24. The video and graphics system of claim 23 wherein the transport processor, the video decoder, and the video compositor are integrated on an integrated circuit chip.

25. The video and graphics system of claim 23 wherein the video data comprises SDTV video data.

26. The video and graphics system of claim 23 wherein the video data comprises HDTV video data.

27. A video decoding system for decoding video data, said system comprising:

at least one decode path for decoding the video data, said at least one decode path comprising a first processing element and a second processing element,

wherein the video data is organized into a plurality of rows, each row comprising a plurality of macroblocks, each macroblock comprising a first portion and a second portion, and said at least one decode path concurrently decodes at least two rows of the video data,

wherein the first processing element decodes the first portion of each macroblock and the second processing element decodes the second portion of each macroblock,

wherein the video data comprises MPEG-2 video data and each row comprises at least one SLICE comprising the macroblocks,

wherein the first processing element decodes the first portion of a first macroblock while the second processing element concurrently decodes the second portion of a second macroblock,

wherein the first macroblock is from a first SLICE and the second macroblock is from a second SLICE, and

wherein the first and second SLICEs are from different rows.