Multibit memory point memory

• US 6,636,434 B2
• Filed: 06/14/2002
• Issued: 10/21/2003
• Est. Priority Date: 06/15/2001
• Status: Active Grant

• Current Assignee: Dolphin Integration
• Original Assignee: Dolphin Integration
• Inventors: Poullet, Frédéric
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/171,607
• Publication Number:
  US 20030086305A1
• Time in Patent Office: 494 Days
• Field of Search: 365/94, 365/103, 365/104, 365/168, 365/189.01, 365/63
• US Class Current: 365/94
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 17/123 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5617 Multilevel ROM cell programmed by source, drain or gate contacting

Abstract

A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2^N connections from among the set of 2^2N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2^N−1 first lines, connect the 2^N−1 other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.

Claims

1. A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>

=2, wherein;

each column includes 2^N conductive lines;

each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2^N connections from among the set of the 2^2N possible connections; and

each of N read means is provided to apply a precharge voltage to a chosen group of 2<sup>N−

1</sup> first lines, connect the 2<sup>N−

1</sup> other lines to a reference voltage, select a memory point, reading the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.

2. The ROM of claim 1, wherein each switch is a MOS transistor, two adjacent transistors of a same column having a common source/drain region.

3. The ROM of claim 2, wherein the gates of the MOS transistors of a same row are interconnected.

4. The ROM of claim 1, wherein each memory point is likely to memorize two bits, in which each column includes four lines respectively called A, B, C, D and in which, for the reading of the first bit, lines A and C are grounded and lines B and D are connected to precharge and read circuits and, for the reading of the second bit, lines A and D are grounded and lines B and C are connected to precharge and read circuits, the connections of the transistors for each of the possible two-bit binary data being given by the following table: