Method and apparatus for processor bypass path to system memory

• US 6,636,939 B1
• Filed: 06/29/2000
• Issued: 10/21/2003
• Est. Priority Date: 06/29/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: George, Varghese
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): LI, ZHUO H
• Application Number:
  US09/607,537
• Time in Patent Office: 1,209 Days
• Field of Search: 711/150, 711/149, 711/100, 711/146, 711/111, 710/107-111, 714/43
• US Class Current: 711/111
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

A memory interface unit is described having a first interface to receive a first request from a processor where the first request has an attribute. The memory interface unit also has a second interface to receive a second request from the processor where the second request does not have the attribute. The memory interface unit also has a third interface to read/write information from/to a system memory. A method is also described that involves forwarding a processor request along a first path to a memory interface unit if the request has one or more attributes; and forwarding the request along a second path to the memory interface unit if the processor request does not have the one or more attributes.

Claims

1. An apparatus, comprising:

a bus interface/L2 cache lookup unit coupled to a first queue to receives requests for instructions, said bus interface/L2 cache lookup unit coupled to a second queue to receive requests for data elements, said bus interfaced/L2 cache lookup unit comprising three separate bus interfaces for three separate busses, said three bus interfaces further comprising;

a) a first bus interface to couple to said L2 cache via a first bus;

b) a second bus interface to couple to a memory interface unit via a second bus;

c) a third bus interface to said memory interface unit via a third bus,

said second bus interface from where those of said requests that;

1) cannot be satisfied by a lookup to L2 cache over said first bus and

2) are characterized according to one or more attributes are sent to said memory interface unit over said second bus after their L2 cache lookup and without crossing said first bus; and

said third bus interface from where those of said requests that;

1), cannot be satisfied by a lookup to L2 cache over said first bus and

2) are not characterized according to said one or more attributes are sent to said memory interface unit over said third bus after their L2 cache lookup and without crossing said first bus.

2. The apparatus of claim 1 wherein said second bus interface is a system bus interface, said second bus being a system bus.

3. The apparatus of claim 1 wherein said second bus interface is a front side bus interface, said second bus being a front side bus.

4. The apparatus of claim 1 wherein said second bus interface further comprises a PCI bus interface, said second bus being a PCI bus.

5. The apparatus of claim 1 wherein said memory interface unit is a memory controller.

6. The apparatus of claim 1 wherein one of said one or more attributes further comprises a read for ownership (RFO) attribute.

7. The apparatus of claim 1 wherein one of said one or more attributes further comprises a self-snoop attribute.

8. The apparatus of claim 1 wherein one of said one or more attributes further comprises a write-back attribute.

9. The apparatus of claim 1 wherein one of said one or more attributes further comprises a system management mode attribute.

10. The apparatus of claim 1 wherein one of said one or more attributes further comprises a locked access attribute.

11. The apparatus of claim 1 wherein said first bus interface is a back side bus interface, said first bus being a back side bus.

12. The apparatus of claim 1 wherein said L2 cache further comprises SRAM memory cells.

13. An apparatus, comprising:

a) a n RDRAM system memory;

b) a system memory interface unit coupled to said system memory; and

c) a bus interface/L2 cache lookup unit coupled to a first queue to receives requests for instructions, said bus interface/L2 cache lookup unit coupled to a second queue to receive requests for data elements, said bus interface/L2 cache lookup unit comprising three separate bus interfaces for three separate busses, said three bus interfaces further comprising;

a) a first bus interface coupled to said L2 cache via a first bus;

b) a second bus interface coupled to said system memory interface unit via a second bus;

c) a third bus interface coupled to said memory interface unit via a third bus,

said second interface from where those of said requests that;

1) cannot be satisfied by a lookup to L2 cache over said first bus and

2) are characterized according to one or more attributes are sent to said system memory interface unit over said second bus after their L2 cache lookup and without crossing said first bus,

said third interface from where those of said requests that;

1) cannot be satisfied by a lookup to L2 cache and

2) are not characterized according to said one or more attributes are sent to said system memory interface unit over said third bus after their L2 cache lookup and without crossing said first bus.

14. The apparatus of claim 13 wherein said second bus interface is a system bus interface, said second bus being a system bus.

15. The apparatus of claim 13 wherein said second bus interface is a front side bus interface, said second bus being a front side bus.

16. The apparatus of claim 13 wherein said second bus interface further comprises a PCI bus interface, said second bus being a PCI bus.

17. The apparatus of claim 13 wherein one of said one or more attributes further comprises a read for ownership (RFO) attribute.

18. The apparatus of claim 13 wherein one of said one or more attributes further comprises a self-snoop attribute.

19. The apparatus of claim 13 wherein one of said one or more attributes further comprises a write-back attribute.

20. The apparatus of claim 13 wherein one of said one or more attributes further comprises a system management mode attribute.

21. The apparatus of claim 13 wherein one of said one or more attributes further comprises a locked access attribute.

22. The apparatus of claim 13 wherein said system memory interface unit is a memory controller.

23. The apparatus of claim 13 wherein said L2 cache further comprises SRAM memory cells.

24. The apparatus of claim 13 wherein said first interface is a back side bus interface, said first bus being a back side bus.

25. A method, comprising:

looking up over a first bus from an L2 cache a first processor request for an instruction or data element;

forwarding said first processor request along a second bus to a memory interface unit so as not to travel across said first bus, if said first request is characterized according to one of one or more attributes and said first request is not satisfied by said L2 cache lookup;

looking up over said first bus from an L2 cache a second processor request for an instruction or data element; and

forwarding said first processor request along a third bus to said memory interface unit so as not to travel across said first bus, if said second request is not characterized according to one of said one or more attributes and said second request is not satisfied by said L2 cache lookup for said second request.

26. The method of claim 25 further comprising queueing said first and second processor request into an outbound queue within said processor prior to said looking up and said forwarding.

27. The method of claim 25 further comprising speculatively preparing a shortcut request to be passed over said third bus for said second processor request while said L2 cache is being said looked up to satisfy said second processor request.

28. The method of claim 27 wherein said forwarding of said second processor request is in response to said L2 cache lookup result indicating that said L2 cache cannot satisfy said second processor request.

29. The method of claim 25 further comprising sending a third requested instruction or data element to said processor if a third processor request for an instruction or data element is found within said L2 cache.

30. The method of claim 25 further comprising reading, with said memory interface unit, said first requested instruction or data element from a memory that is coupled to said memory interface unit.

31. The method of claim 30 further comprising reading, with said memory interface unit, said second requested instruction or data element from said memory.

32. The method of claim 31 further comprising forwarding said second requested instruction or data to said processor.

33. The method of claim 27 wherein one of said one or more attributes further comprises a read for ownership (RFO) attribute.

34. The method of claim 27 wherein one of said one or more attributes further comprises a self-snoop attribute.

35. The method of claim 27 wherein one of said one or more attributes further comprises a write-back attribute.

36. The method of claim 27 wherein one of said one or more attributes further comprises a system management mode.

37. The method of claim 27 wherein one of said one or more attributes further comprises a locked access attribute.

38. An apparatus, comprising:

a semiconductor chip comprising a processor and circuitry to retrieve requests for data elements made by said processor and requests for instructions made by said processor, said circuitry comprising;

a) a back side bus interface to communicate with a cache via a back side bus that is coupled to said back side bus interface;

b) a front side bus interface to communicate with a memory controller via a front side bus that is coupled to said front side bus interface and that is separate from said back side bus, said front side bus interface to send to said memory controller-over said front side bus and not over said back side bus those of said requests characterized by one or more attributes that were not satisfied by a lookup to said cache;

c) a shortcut bus interface to communicate with said memory controller without communicating over said front side bus or said back side bus via a shortcut bus that is coupled to said memory controller, said shortcut bus separate from said back side bus and said front side bus, said shortcut bus interface to send to said memory controller over said shortcut bus and not over said back side bus those of said requests not characterized by said one or more attributes that were not satisfied by a lookup to said cache.

39. The apparatus of claim 38 wherein said circuitry further comprises policing logic circuitry that speculatively prepares a communication for transmission through said shortcut bus interface for those of said requests not characterized by said one or more attributes prior to it being known whether they will be satisfied by their corresponding cache lookup.

40. The apparatus of claim 38 wherein one of said one or more attributes further comprises a read for ownership (RFO) attribute.

41. The apparatus of claim 38 wherein one of said one or more attributes further comprises a self-snoop attribute.

42. The apparatus of claim 38 wherein one of said one or more attributes further comprises a write-back attribute.

43. The apparatus of claim 38 wherein one of said one or more attributes further comprises a system management mode attribute.

44. The apparatus of claim 38 wherein one of said one or more attributes further comprises a locked access attribute.

46. The machine readable medium of claim 38 wherein one of said one or more attributes further comprises a read for ownership (RFO) attribute.

47. The machine readable medium of claim 38 wherein one of said one or more attributes further comprises a self-snoop attribute.

48. The machine readable medium of claim 38 wherein one of said one or more attributes further comprises a write-back attribute.

49. The machine readable medium of claim 38 wherein one of said one or more attributes further comprises a system management mode attribute.

50. The machine readable medium of claim 38 wherein one of said one or more attributes further comprises a locked access attribute.

45. A machine readable medium containing a description of semiconductor chip circuit design, said semiconductor chip circuit design comprising a design for:

a processor and circuitry to retrieve requests for data elements made by said processor and requests for instructions made by said processor, said circuitry comprising;

a) a back side bus interface to communicate with a cache via a back side bus that is coupled to said back side bus interface;

b) a front side bus interface to communicate with a memory controller via a front side bus that is coupled to said front side bus interface and that is separate from said back side bus, said front side bus interface to send to said memory controller over said front side bus and not over said back side bus those of said requests characterized by one or more attributes that were not satisfied by a lookup to said cache;

c) a shortcut bus interface to communicate with said memory controller without communicating over said front side bus or said back side bus via a shortcut bus that is coupled to said memory controller, said shortcut bus separate from said back side bus and said front side bus, said shortcut bus interface to send to said memory controller over said shortcut bus and not over said back side bus those of said requests not characterized by said one or more attributes that were not satisfied by a lookup to said cache.