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Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

  • US 6,636,955 B1
  • Filed: 08/31/2000
  • Issued: 10/21/2003
  • Est. Priority Date: 08/31/2000
  • Status: Expired due to Fees
First Claim
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1. A memory controller, comprising:

  • a plurality of multi-entry read buffers each adapted to be coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command;

    a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded;

    a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; and

    each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers;

    wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing;

    wherein each load pointer logic circuit increments its load pointer using a clock to master clock that is provided and routed by the memory controller to the memory modules and back to the memory controller.

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