Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

• US 6,636,955 B1
• Filed: 08/31/2000
• Issued: 10/21/2003
• Est. Priority Date: 08/31/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Baum, Allen J., Breach, Scott E., Bouchard, Gregg A., Kessler, Richard E., Steinman, Maurice B., Bannon, Peter J.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Choi, Woo H.
• Application Number:
  US09/652,480
• Time in Patent Office: 1,146 Days
• Field of Search: 711/5, 711/154, 711/166, 711/167, 711/219, 710/25, 710/52, 710/310
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

Claims

1. A memory controller, comprising:

a plurality of multi-entry read buffers each adapted to be coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command;

a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded;

a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; and

each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers;

wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing;

wherein each load pointer logic circuit increments its load pointer using a clock to master clock that is provided and routed by the memory controller to the memory modules and back to the memory controller.

2. A method to initialize a memory controller coupled to a plurality of memory modules via a plurality of memory channels, comprising:

writing a predetermined bit pattern to each memory channel for storage in the memory modules;

for each memory channel, keeping load and unload pointers associated with a read buffer from incrementing;

issuing a read command to cause the memory modules to provide the predetermined bit pattern back to the memory controller over the memory channels;

for each memory channel, detecting that the requested bit pattern has begun to arrive over the memory channel and then releasing that channel'"'"'s load pointer to begin incrementing in accordance with a source synchronous clock signal.

3. The method of claim 2 further including:

counting a predetermined amount of time after issuing the read command to the memory channels; and

releasing all of the unload pointers associated with the read buffers in all of the memory channels to increment in accordance a clock signal that is different than said source synchronous clock signal.

4. The method of claim 3 wherein said predetermined amount of time is substantially the maximum skew time associated with the memory channels.

5. A computer system, comprising:

a CPU core;

an I/O device coupled to said CPU core; and

a memory controller coupled to a plurality of memory modules, including;

a plurality of multi-entry read buffers each adapted to be coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command;

a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded;

a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; and

each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers;

wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization, when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus, the load pointer is released and begins incrementing; and

wherein each load pointer logic circuit increments its load pointer using a clock to master clock that is provided and routed by the memory controller to the memory modules and back to the memory controller.