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Method and program for processing design pattern of semiconductor integrated circuit

  • US 6,637,010 B2
  • Filed: 09/27/2001
  • Issued: 10/21/2003
  • Est. Priority Date: 09/27/2000
  • Status: Expired due to Fees
First Claim
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1. A method for processing design pattern data of a semiconductor integrated circuit, comprising:

  • determining whether there are lower-level cells whose individual size is equal to or below a threshold;

    if there are such lower-level cells whose individual size is equal to or below the threshold, pairing a first lower-level cell with a second lower-level cell, that is adjacent to the first lower-level cell, to define a new cell whose size is greater than the threshold; and

    replacing the first and second lower-level cells with the new cell.

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