Methods of forming semiconductor constructions

• US 6,638,834 B2
• Filed: 10/15/2002
• Issued: 10/28/2003
• Est. Priority Date: 06/12/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Le, Thao P
• Application Number:
  US10/271,888
• Publication Number:
  US 20030059999A1
• Time in Patent Office: 378 Days
• Field of Search: 438/205, 438/197, 438/199, 438/202
• US Class Current: 438/455
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface.

Claims

1. A method of forming a semiconductor construction, comprising:

forming a first semiconductor substrate comprising a first monocrystalline base and having a first transistor supported on the first monocrystalline base;

the first transistor having source/drain regions associated therewith;

the first substrate also having an insulative material formed over the base and silicon-containing plugs extending through the insulative material and to the source/drain regions;

the silicon-containing plugs being separated from one another by the insulative material and defining a planarized upper surface above the first monocrystalline base;

providing a second semiconductor substrate comprising a second monocrystalline base and bonding the second semiconductor substrate to the silicon-containing plugs at the planarized upper surface above the first monocrystalline base; and

forming a second transistor supported over the second substrate.

2. The method of claim 1 wherein one of the first and second transistors is a PMOS transistor and wherein the other of the first and second transistors is an NMOS transistor.

3. The method of claim 1 wherein the second transistor comprises source/drain regions which extend entirely through the second monocrystalline base.

4. The method of claim 1 wherein the second transistor comprises source/drain regions which extend only partially through the second monocrystalline base.

5. A method of forming a semiconductor construction, comprising:

forming a first substrate comprising silicon-containing structures separated from one another by an insulative material;

the silicon-containing structures defining an upper surface;

bonding a second semiconductor substrate to the silicon-containing structures at the upper surface;

the second semiconductor substrate comprising a monocrystalline material which is bonded to the silicon-containing structures; and

forming at least one doped silicon region extending through the monocrystalline material and electrically contacting at least one of the silicon-containing structures.

6. The method of claim 5 wherein the forming the at least one doped silicon region comprises implanting dopant into the monocrystalline material.

7. The method of claim 5 further comprising forming at least one insulative region extending at least partially into the monocrystalline material.

8. The method of claim 5 further comprising forming at least one insulative region extending through the monocrystalline material.

9. The method of claim 8 wherein the forming the at least one insulative region comprises:

forming an opening through the monocrystalline material; and

filling the opening with an insulative material.

10. The method of claim 5 wherein the forming the at least one doped silicon region comprises:

forming an opening through the monocrystalline material; and

filling the opening with a doped silicon material.

11. The method of claim 10 wherein the doped silicon material comprises doped amorphous silicon.

12. The method of claim 10 wherein the doped silicon material comprises doped polycrystalline silicon.

13. The method of claim 5 further comprising forming at least one second doped silicon region within the second monocrystalline base and which does not extend entirely through the second monocrystalline base.

14. The method of claim 13 wherein the forming the at least one doped silicon region comprises:

forming an opening through the monocrystalline material; and

filling the opening with a doped silicon material.

15. The method of claim 14 wherein the doped silicon material comprises doped amorphous silicon.

16. The method of claim 14 wherein the doped silicon material comprises doped polycrystalline silicon.