Semiconductor structure including a partially annealed layer and method of forming the same

• US 6,638,838 B1
• Filed: 10/02/2000
• Issued: 10/28/2003
• Est. Priority Date: 10/02/2000
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Foley, Barbara M., Thompson, Danny L., Eisenbeiser, Kurt, Finder, Jeffrey M.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/678,372
• Time in Patent Office: 1,121 Days
• Field of Search: 438/479, 438/480, 438/481, 438/606, 438/607, 438/763, 117/101, 117/105, 117/108
• US Class Current: 438/481
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02521 Materials

Abstract

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.

Claims

1. A process for fabricating a semiconductor structure, comprising:

exposing a (100) surface of a monocrystalline silicon substrate, said surface comprising strontium and silicon, to strontium, titanium and oxygen while varying a partial pressure of oxygen so as to

     1) epitaxially grow a 2 to 100 nm thick ordered monocrystalline layer of strontium titanate having a (100) crystal orientation rotated by 45°

with respect to the (100) surface of the monocrystalline silicon substrate and

     2) form an amorphous silicon oxide layer at the interface between the silicon substrate and the growing strontium titanate layer;

forming, on the monocrystalline layer of strontium titanate, a template layer of Ti—

As, Sr—

O—

As, Sr—

Ga—

O or Sr—

Al—

O; and

exposing the template layer to gallium and arsenic to epitaxially grow a monocrystalline (100) GaAs layer on the monocrystalline layer of strontium titanate,

wherein said partial pressure of oxygen is initially set at a value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute and, after initiating growth of strontium titanate, the partial pressure of oxygen is increased above said value to cause growth of said amorphous silicon oxide layer at the interface between the silicon substrate and the growing strontium titanate layer.

2. The process of claim 1, wherein said structure is a wafer.

3. The process of claim 1, wherein said structure is a light emitting diode.

4. The process of claim 1, wherein said structure is a laser.

5. The process of claim 1, wherein said template layer is a layer of Ti—

As.