Method for preventing or reducing anodic Cu corrosion during CMP

• US 6,638,868 B1
• Filed: 05/07/2002
• Issued: 10/28/2003
• Est. Priority Date: 05/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hung, Kun Ku, Chiou, Wen-Chin, Tung, Wen-Hun, Shih, Tsu
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Isaac, Stanetta
• Application Number:
  US10/141,221
• Publication Number:
  US 20030211744A1
• Time in Patent Office: 539 Days
• Field of Search: 156/345.55, 257/330, 257/332, 438/270, 438/271
• US Class Current: 438/692
• CPC Class Codes: B24B 37/042 operating processes therefor
• CPC Class Codes: B24B 37/046 using electric current
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

A method and apparatus for implementing the method for preventing or reducing corrosion of copper containing features included in a semiconductor wafer in a chemical mechanical polishing (CMP) process the method providing at least one semiconductor wafer polishing surface including copper filled anisotropically etched features; polishing the at least one semiconductor wafer polishing surface according to a CMP process having a polishing pad surface contacting the at least one it semiconductor wafer polishing surface at least a portion of the polishing pad in electrically conductive communication with a conductive polishing platen; and, providing at least one electrically conductive pathway from the conductive polishing platen.

Claims

1. A method for preventing or reducing corrosion of copper containing features included in a semiconductor wafer in a chemical mechanical polishing (CMP) process comprising the steps of:

providing at least one semiconductor wafer polishing surface including copper filled features;

polishing the at least one semiconductor wafer polishing surface according to a CMP process having a polishing pad surface contacting the at least one semiconductor wafer polishing surface at least a portion of the polishing pad in electrically conductive communication with a conductive polishing platen; and

,

providing at least one electrically conductive pathway comprising an electrical contact member for maintaining continuous contact with a portion of the conductive polishing platen to maintain continuous electrical communication from the semiconductor wafer polishing surface to ground potential during the CMP process to reduce an electrical charge at the at least one semiconductor wafer polishing surface.

2. The method of claim 1, wherein the at least a portion of the polishing pad is attached to the conductive polishing platen by an electrically conductive adhesive.

3. The method of claim 1, wherein the electrical contact member is positioned to provide electrically conductive contact with a peripheral portion of the conductive polishing platen.

4. The method of claim 1, wherein the electrical contact member is maintained linearly stationary with respect to a motion of the conductive polishing platen during the CMP process.

5. The method of claim 4, wherein a contact friction between the electrical contact member and the conductive polishing platen is minimized by rotary motion of the electrical contact member in response to the motion of the conductive polishing platen.

6. The method of claim 1, wherein the at least a portion of the CMP process includes at least partially polishing a barrier/adhesion layer underlying a copper layer at the at A least one semiconductor wafer polishing surface.

7. The method of claim 1, wherein the step of providing at least one electrically conductive pathway from the conductive polishing platen to ground potential includes providing the at least one electrically conductive pathway proximal to the at least one semiconductor wafer polishing surface.

8. The method of claim 1, wherein the step of providing at least one electrically conductive pathway includes reducing an electrically conductive pathway resistance to ground potential to remove a substantial portion of an electrical charge at the at least one semiconductor wafer polishing surface.

9. The method of claim 1, wherein the conductive polishing platen moves in at least one of a rotary and linear motion with respect to the semiconductor wafer polishing surface during the CMP process.

10. The method of claim 9, wherein the conductive polishing platen comprises one of a linear and rotary chemical mechanical polisher.

11. The method of claim 1, wherein the electrical contact member comprises at least one rotary means maintained in continuous contact according to an applied force.

12. The method of claim 1, wherein the electrical charge comprises electrostatic charge.

13. The method of claim 1, wherein the step of providing at least one electrically conductive pathway comprises reducing anodic corrosion of the copper filled features.

14. The method of claim 1, wherein the copper filled features are dual damascene features.