High-voltage transistor with multi-layer conduction region

• US 6,639,277 B2
• Filed: 09/20/2001
• Issued: 10/28/2003
• Est. Priority Date: 11/05/1996
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Rumennik, Valdimir, Disney, Donald R., Ajit, Janardhanan S.
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US09/961,235
• Publication Number:
  US 20020050613A1
• Time in Patent Office: 768 Days
• Field of Search: 257/262, 257/328, 257/314, 257/339-344, 257/492-495, 257/488
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0852 of DMOS transistors
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Claims

1. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type;

a source diffusion region of the second conductivity type disposed in the substrate spaced-apart from the first region to form an IGFET channel region therebetween;

a drain diffusion region disposed in the first region;

a first plurality of vertically spaced-apart buried layers of the first conductivity type disposed within the first region and spaced-apart from the drain diffusion region, the buried layers extending continuously across a portion of the first region to form an associated plurality of JFET channels in the first region, each of the buried layers having a length and a width the length being substantially greater than the width;

an insulating layer disposed over the substrate; and

a gate overlying an area of the insulating layer above the IGFET channel region.

2. The HVFET according to claim 1 further comprising:

a second region of the first conductivity type disposed in the substrate adjacent the source diffusion region.

3. The HVFET according to claim 1 further comprising:

a source electrode connected to the source diffusion region; and

a drain electrode connected to the drain diffusion region.

4. The HVFET according to claim 3 wherein the source electrode includes a first field plate member that extends over the gate.

5. The HVFET according to claim 4 wherein the drain electrode includes a second field plate member.

6. The HVFET according to claim 1 wherein the first region comprises an epitaxial layer disposed on the substrate.

7. The HVFET according to claim 1 wherein the first region comprises a well region disposed in the substrate.

8. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type;

a source diffusion region of the second conductivity type disposed in the substrate spaced-apart from the first region to form an IGFET channel region therebetween;

a drain diffusion region disposed in the first region;

a first plurality of buried layers of the first conductivity type disposed within the first region spaced-apart from the drain diffusion region, the first plurality of buried layers forming an associated plurality of JFET channels in the first region;

a second plurality of buried layers of the first conductivity type disposed beneath the source diffusion region;

an insulating layer disposed over the substrate; and

a gate overlying an area of the insulating layer above the IGFET channel region.

9. The HVFET according to claim 8 wherein the second plurality of buried layers extend under the IGFET channel region.

10. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type disposed within the substrate;

a source diffusion region of the second conductivity type disposed in the substrate spaced-apart from the first region, a channel region being formed in the substrate between the source diffusion region and the first region;

a source electrode connected to the source diffusion region;

a drain diffusion region of the second conductivity type disposed within the first region;

a drain electrode connected to the drain diffusion region;

a plurality of vertically spaced-apart buried regions of the first conductivity type disposed within the first region, all but one of the buried regions not being in contact with a too surface of the substrate, the buried regions each being spaced-apart from the drain diffusion region and extending continuously across a portion of the first region to form a corresponding plurality of conduction channels, each of the buried regions having a length and a width, the length being substantially greater than the width; and

an insulated gate formed over the channel region.

11. The HVFET according to claim 10 further comprising:

a second region of the first conductivity type disposed within the substrate, the source diffusion region being disposed within the second region.

12. The HVFET according to claim 11 further comprising

a third region of the first conductivity type disposed in the second region adjacent to the source diffusion region.

13. The HVFET according to claim 10 wherein the buried regions are connected to the substrate.

14. The HVFET according to claim 10 further comprising:

the at least one second buried region of the first conductivity type disposed within substrate beneath the source diffusion region.

15. The HVFET according to claim 14 wherein the at least one second buried region extends laterally from the source diffusion region under the channel region.

16. The HVFET according to claim 10 wherein the first and second conductivity types are p-type and n-type, respectively.

17. The HVFET according to claim 10 wherein the source and drain electrodes include field plate members.

18. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type;

a source region of the second conductivity type separated from the first region;

a drain region disposed in the first region;

a plurality of buried layers of the first conductivity type disposed within the first region and vertically separated from each other, the plurality of buried layers extending continuously across a portion of the first region to form an associated plurality of conduction channels in the first region, each of the buried layers having a length and a width, the length being substantially greater than the width; and

an insulated gate extending from the source region to the first region.

19. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type;

a source region of the second conductivity type separated from the first region;

a drain region disposed in the first region;

a plurality of buried layers of the first conductivity type disposed within the first region and vertically separated from each other, each of the buried layers extending continuously across a portion of the first region, each of the buried layers having a length and a width, the length being substantially greater than the width; and

an insulated extending from the source region to the first region.