Multi-layer inductor formed in a semiconductor substrate

• US 6,639,298 B2
• Filed: 10/05/2001
• Issued: 10/28/2003
• Est. Priority Date: 06/28/2001
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Griglione, Michelle D., Laradji, Mohamed, Chaudhry, Samir, Thomson, J. Ross, Layman, Paul Arthur
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US09/972,482
• Publication Number:
  US 20030001231A1
• Time in Patent Office: 753 Days
• Field of Search: 257/531, 257/758
• US Class Current: 257/531
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A thin-film multi-layer high Q inductor spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical communications with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The plurality of first metal runners are in a different vertical than the plurality of second metal runners such that the planes intersect. Thus one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias., forming a continuously conductive structure having a generally helical shape.

Claims

1. An integrated circuit inductor structure comprising:

a semiconductor substrate having a plurality of insulating layers and a plurality of metallization layers therebetween;

a plurality of first conductive strips disposed in a first metallization layer of said semiconductor substrate;

a first stack of conductive vias in electrical connection with a first end of each one of the plurality of first conductive strips;

a second stack of conductive vias in electrical connection with a second end of each one of the plurality of first conductive strips; and

a plurality of second conductive strips disposed in a second metallization layer of said semiconductor substrate, wherein one of the plurality of second conductive strips spans and interconnects two consecutive first conductive strips through the first and the second stack of conductive vias, and wherein each one of the plurality of second conductive strips has a first end in electrical connection with an upper surface of the first stack of conductive vias and a second end in electrical connection with an upper surface of the second stack of conductive vias for interconnecting the two consecutive first conductive strips, wherein the plurality of second conductive strips are vertically spaced-apart from the plurality of first conductive strips with at least three intervening metallization layers therebetween.

2. A multi-level integrated circuit inductor structure, comprising:

a semiconductor substrate having a plurality of insulating layers and a plurality of conductive layers therebetween, and further having a plurality of active devices formed therein;

runner conductive portions including first and second terminal ends thereof, wherein each of the first and the second terminal ends is connected to one of the plurality of active devices;

vertical conductive portions;

wherein lower runner portions are formed in a lower conductive layer of the semiconductor substrate;

wherein upper runner portions are formed at least two or more conductive layers above the lower runner portions;

wherein two or more vertically aligned first via portions effect electrical connection between a first end of a first lower runner portion and an overlying first end of a first upper runner portion; and

wherein two or more vertically aligned second via portions effect electrical connection between a first end of a second lower runner portion and an overlying second end of the first upper runner portion.