Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries

• US 6,639,302 B2
• Filed: 03/20/2002
• Issued: 10/28/2003
• Est. Priority Date: 03/20/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Woychik, Charles G., Darbha, Krishna, Jimarez, Miguel A., Sathe, Sanjeev B., Reiss, Matthew M.
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/103,602
• Publication Number:
  US 20030178649A1
• Time in Patent Office: 587 Days
• Field of Search: 257/620
• US Class Current: 257/620
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Claims

1. An electronic structure, comprising:

a chip carrier, wherein the chip carrier is selected from the group consisting of a ceramic chip carrier and an organic chip carrier, and wherein the chip carrier is divided into a plurality of lateral segments, and

a semiconductor device, wherein discrete sections of the semiconductor device are electrically coupled to each of the segments.

2. The electronic structure of claim 1, wherein the discrete sections of the semiconductor device are symmetrically coupled to each segment.

3. The electronic structure of claim 1, wherein the discrete sections of the semiconductor device are not symmetrically coupled to each segment.

4. The electronic structure of claim 1, wherein a first segment and a second segment of the plurality of segments are congruent with respect to each other.

5. The electronic structure of claim 1, wherein a first segment and a second segment of the plurality of segments are not congruent with respect to each other.

6. The electronic structure of claim 1, wherein the plurality of segments are square segments.

7. The electronic structure of claim 1, wherein the plurality of segments consists of 4 segments.

8. The electronic structure of claim 1, wherein the semiconductor device is a semiconductor chip.

9. A method for forming an electronic structure, comprising:

dividing a substrate into a plurality of lateral segments, wherein the substrate is selected from the group consisting of a ceramic chip carrier, an organic chip carrier, and a printed circuit board, and

electrically coupling discrete sections of the semiconductor device to each segment of the plurality of segments of the substrate.

10. The method of claim 9, wherein the semiconductor device is symmetrically coupled to each segment.

11. The method of claim 9, wherein the semiconductor device is not symmetrically coupled to each segment.

12. The method of claim 9, wherein a first segment and a second segment of the plurality of segments are congruent with respect to each other.

13. The method of claim 9, wherein a first segment and a second segment of the plurality of segments are not congruent with respect to each other.

14. The method of claim 9, wherein the plurality of segments consists of 4 segments.

15. The method of claim 10, wherein the plurality of segments are square segments.

16. The method of claim 9, wherein the substrate is an organic chip carrier.

17. The method of claim 9, wherein the substrate is a ceramic chip carrier.

18. The method of claim 9, wherein the substrate is a printed circuit board.

19. An electronic structure, comprising:

a printed circuit board, wherein the printed circuit board is divided into a plurality of lateral segments, and

a semiconductor device, wherein discrete sections of the semiconductor device are electrically coupled to each of the segments.

20. The electronic structure of claim 19, wherein the discrete sections of the semiconductor device are symmetrically coupled to each segment.

21. The electronic structure of claim 19, wherein the discrete sections of the semiconductor device are not symmetrically coupled to each segment.

22. The electronic structure of claim 19, wherein a first segment and a second segment of the plurality of segments are congruent with respect to each other.

23. The electronic structure of claim 19, wherein the plurality of segments are square segments.

24. The electronic structure of claim 19, wherein the plurality of segments consists of 4 segments.

25. The electronic structure of claim 19, wherein the semiconductor device is a semiconductor chip.