Motor and disk drive apparatus

• US 6,639,372 B2
• Filed: 04/24/2002
• Issued: 10/28/2003
• Est. Priority Date: 12/06/1999
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Gotou, Makoto
• Primary Examiner(s): Ro, Bentsu
• Assistant Examiner(s): Duda, Rina I.
• Application Number:
  US10/132,814
• Publication Number:
  US 20020117981A1
• Time in Patent Office: 552 Days
• Field of Search: 318/254, 318/439, 318/138, 318/811, 318/599, 318/430-434
• US Class Current: 318/400.32
• CPC Class Codes: H02P 6/085 in a bridge configuration

Abstract

A motor comprising: Q-phase windings; voltage supplying unit; power supplying unit having Q first power transistors and Q second power transistors for supplying a power to said Q-phase windings; voltage detecting unit; state shifting unit; activation control unit; and switching operation unit. The switching operation unit includes switching control circuit for producing a main switching pulse and an auxiliary switching pulse, said switching operation circuit executing high-frequency switching operation of at least one second power transistor among said Q second power transistors responding with said auxiliary switching pulse signal when two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while at least another second power transistor among said Q second power transistors executes an ON operation.

Claims

1. A motor comprising:

a rotor which has a field part generating field fluxes;

Q-phase windings, Q being an integer of three or more;

voltage supplying means which includes two output terminals for supplying a DC voltage;

power supplying means having Q first power transistors and Q second power transistors for supplying a power to said Q-phase windings, each of said Q first power transistors forming a current path between one output terminal side of said voltage supplying means and one of said Q-phase windings, and each of said Q second power transistors forming a current path between the other output terminal side of said voltage supplying means and one of said Q-phase windings;

voltage detecting means for producing a detected pulse signal responding with terminal voltages of said Q-phase windings;

state shifting means for shifting a holding state from one state to at least one other state in sequence responding with the detected pulse signal of said voltage detecting means;

activation control means for controlling active periods of said Q first power transistors and said Q second power transistors responding with said holding state; and

switching operation means for causing at least one power transistor among said Q first power transistors and said Q second power transistors to perform high-frequency switching corresponding to a command signal;

and that

said state shifting means shifts said holding state from a first state to a second state after a first adjust time from detection of said detected pulse signal, and further shifts said holding state from said second state to a third state after a second adjust time from detection of said detected pulse signal, said second adjust time being larger than said first adjust time;

said activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with said holding state of said state shifting means or controlling said active periods of said Q first power transistors and said Q second power transistors, each of said active periods being larger than the period of 360/Q electrical degrees; and

said switching operation means includes;

current detecting means for producing a current detected signal which responds with or corresponds to a current from said voltage supplying means to said Q-phase windings; and

switching control means for producing a main switching pulse signal and an auxiliary switching pulse signal which respond with said current detected signal and said command signal, providing a time between an effective period of said main switching pulse signal and an effective period of said auxiliary switching pulse signal, causing at least one of said Q first power transistors to become ON in the effective period of said main switching pulse signal, causing at least one of said Q second power transistors to become ON in the effective period of said auxiliary switching pulse signal, and executing high-frequency switching operation of at least one second power transistor among said Q second power transistors responding with said auxiliary switching pulse signal when two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while at least another second power transistor among said Q second power transistors executes ON operation.

2. The motor in accordance with the claim 1, wherein

said switching control means executes high-frequency switching operation of two second power transistors among said Q second power transistors simultaneously responding with said auxiliary switching pulse signal when said two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while said at least another second power transistor among said Q second power transistors executes ON operation.

3. The motor in accordance with the claim 1, wherein

said state shifting means produces said first adjust time and said second adjust time substantially proportional to an interval of said detected pulse signal.

4. The motor in accordance with the claim 1, wherein

said voltage detecting means stops detecting of said detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of said at least one power transistor and a second stop period including another changing timing from ON to OFF of said at least one power transistor, and executes detecting of said detected pulse signal during at least ON period of said at least one power transistor excluding said at least one of said first stop period and said second stop period, thereby producing said detected pulse signal which responds with terminal voltages of said Q-phase windings.

5. The motor in accordance with claim 4, wherein said voltage detecting means stops detecting of said detected pulse signal during both of said first stop period and said second stop period, and executes detecting of said detected pulse signal during a rest period excluding said both of said first stop period and said second stop period, thereby producing said detected pulse signal which responds with terminal voltages of said Q-phase windings.

6. The motor in accordance with claim 4, wherein

said voltage detecting means includes:

voltage comparing means for producing an output signal which responds with comparison result of terminal voltages of said Q-phase windings; and

noise eliminating means for gating the output signal of said voltage comparing means with a noise eliminating signal which responds or corresponds with said switching pulse signal, so as not to pass the output signal of said voltage comparing means during at least one of a first period including a changing timing from OFF to ON of said switching pulse signal and a second period including another changing timing from ON to OFF of said switching pulse signal.

7. The motor in accordance with claim 6, wherein

said voltage detecting means further includes;

pulse producing means having a flip-flop circuit for changing a state of said flip-flop circuit with a rising or falling edge of an output signal of said noise eliminating means and producing said detected pulse signal which responds with the state of said flip-flop circuit.

8. The motor in accordance with claim 4, wherein

said voltage detecting means stops detecting of said detected pulse signal from a pulse timing of said detected pulse signal to a third adjust time, said third adjust time being larger than said second adjust time and substantially proportional to an interval of said detected pulse signal.

9. The motor in accordance with claim 1, further comprising

commanding means for producing said command signal which responds with an output pulse signal of said voltage detecting means.

10. A motor comprising:

a rotor which has a field part generating field fluxes;

Q-phase windings, Q being an integer of 3 or more;

voltage supplying means which includes two output terminals for supplying a DC voltage;

power supplying means having Q first power transistors and Q second power transistors for supplying a power to said Q-phase windings, each of said Q first power transistors forming a current path between one output terminal side of said voltage supplying means and one of said Q-phase windings, and each of said Q second power transistors forming a current path between the other output terminal side of said voltage supplying means and one of said Q-phase windings;

activation control means for controlling said Q first power transistors and said Q second power transistors; and

switching operation means for causing at least one power transistor among said Q first power transistors and said Q second power transistors to perform high-frequency switching corresponding to a command signal;

and that

said activation control means determines active periods of said Q first power transistors and said Q second power transistors, each of said active periods being larger than the period of 360/Q electrical degrees, and

said switching operation means includes;

current detecting means for producing a current detected signal which responds with or corresponds to a current from said voltage supplying means to said Q-phase windings, and

switching control means for producing a main switching pulse signal and an auxiliary switching pulse signal which respond with said current detected signal and said command signal, providing a time between an effective period of said main switching pulse signal and an effective period of said auxiliary switching pulse signal, causing at least one of said Q first power transistors to become ON in the effective period of said main switching pulse signal, causing at least one of said Q second power transistors to become ON in the effective period of said auxiliary switching pulse signal, and executing high-frequency switching operation of at least one second power transistor among said Q second power transistors responding with said auxiliary switching pulse signal when two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while at least another second power transistor among said Q second power transistors executes ON operation.

11. The motor in accordance with claim 10, wherein

said switching control means executes high-frequency switching operation of two second power transistors among said Q second power transistors simultaneously responding with said auxiliary switching pulse signal when said two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while said at least another second power transistor among said Q second power transistors executes ON operation.

12. The motor in accordance with claim 10, wherein

said activation control means produces Q-phase first activation signals, each of which has an active period larger than 360/Q degree and responds with said main switching pulse signal, so as to control said Q first power transistors, and produces Q-phase second activation control signals, each of which has an active period larger than 360/Q degree and responds with said auxiliary switching pulse signal, so as to control said Q second power transistors.

13. The motor in accordance with the claim 10, wherein

said voltage detecting means stops detecting of said detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of said at least one power transistor and a second stop period including another changing timing from ON to OFF of said at least one power transistor, and executes detecting of said detected pulse signal during at least ON period of said at least one power transistor excluding said at least one of said first stop period and said second stop period, thereby producing said detected pulse signal which responds with terminal voltages of said Q-phase windings.

14. A disk drive apparatus comprising:

a head for at least reproducing a signal from a disk or recording a signal on a disk;

processing means for at least processing an output signal from said head and outputting a reproducing information signal, or processing a recording information signal and outputting a signal into said head;

a rotor which has a field part generating field fluxes, and directly drives said disk;

Q-phase windings, Q being an integer of 3 or more;

voltage supplying means which include two output terminals for supplying a DC voltage;

power supplying means having Q first power transistors and Q second power transistors for supplying a power to said Q-phase windings, each of said Q first power transistors forming a current path between one output terminal side of said voltage supplying means and one of said Q-phase windings, and each of said Q second power transistors forming a current path between the other output terminal side of said voltage supplying means and one of said Q-phase windings;

voltage detecting means for producing a detected pulse signal responding with terminal voltages of said Q-phase windings;

state shifting means for shifting a holding state from one state to at least one other state in sequence responding with the detected pulse signal of said voltage detecting means;

activation control moans for controlling active periods of said Q first power transistors and said Q second power transistors responding with said holding state; and

switching operation means for causing at least one power transistor among said Q first power transistors and said Q second power transistors to perform high-frequency switching corresponding to a command signal;

and that

said state shifting means shifts said holding state from a first state to a second state after a first adjust time from detection of said detected pulse signal, and further shifts said holding state from said second state to a third state after a second adjust time from detection of said detected pulse signal, said second adjust time being larger than said, first adjust time,

said activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with said holding state of said state shifting means for controlling said active periods of said Q first power transistors and said Q second power transistors, each of said active periods being larger than the period of 360/Q electrical degrees, and

said switching operation means includes;

current detecting means for producing a current detected signal which responds with or corresponds to a current from said voltage supplying means to said Q-phase windings, and

switching control means for producing a main switching pulse signal and an auxiliary switching pulse signal which respond with said current detected signal and said command signal, providing a time between an effective period of said main switching pulse signal and an effective period of said auxiliary switching pulse signal, causing at least one of said Q first power transistors to become ON in the effective period of said main switching pulse signal, causing at least one of said Q second power transistors to become ON in the effective period of said auxiliary switching pulse signal, and executing high-frequency switching operation of at least one second power transistor among said Q second power transistors responding with said auxiliary switching pulse signal when two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while at least another second power transistor among said Q second power transistors executes ON operation.

15. The disk drive apparatus in accordance with claim 14, wherein

said switching control means executes high-frequency switching operation of two second power transistors among said Q second power transistors simultaneously responding with said auxiliary switching pulse signal when said two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while said at least another second power transistor among said Q second power transistors executes ON operation.

16. The disk drive apparatus in accordance with claim 14, wherein

said state shifting means produces said first adjust time and said second adjust time substantially proportional to an interval of said detected pulse signal.

17. The disk drive apparatus in accordance with claim 14, wherein

said voltage detecting means stops detecting of said detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of said at least one power transistor and a second stop period including another changing timing from ON to OFF of said at least one power transistor, and executes detecting of said detected pulse signal during at least ON period of said at least one power transistor excluding said at least one of said first stop period and said second stop period, thereby producing said detected pulse signal which responds with terminal voltages of said Q-phase windings.

18. The disk drive apparatus in accordance with claim 17, wherein

said voltage detecting means stops detecting of said detected pulse signal during both of said first stop period and said second stop period, and executes detecting of said detected pulse signal during a rest period excluding said both of said first stop period and said second stop period, thereby producing said detected pulse signal which responds with terminal voltages of said Q-phase windings.

19. The disk drive apparatus in accordance with claim 17, wherein

said voltage detecting means includes:

voltage comparing means for producing an output signal which responds with comparison result of terminal voltages of said Q-phase windings, and

noise eliminating means for gating the output signal of said voltage comparing means with a noise eliminating signal which responds or corresponds with said switching pulse signal, so as not to pass the output signal of said voltage comparing means during at least one of a first period including a changing timing from OFF to ON of said switching pulse signal and a second period including another changing timing from ON to OFF of said switching pulse signal.

20. The disk drive apparatus in accordance with claim 19, wherein

said voltage detecting means further includes:

pulse producing means having a flip-flop circuit for changing a state of said flip-flop circuit with a rising or falling edge of art output signal of said noise eliminating means and producing said detected pulse signal which responds with the state of said flip-flop circuit.

21. The disk drive apparatus in accordance with claim 17, wherein

said voltage detecting means stops detecting of said detected pulse signal from a pulse timing of said detected pulse signal to a third adjust time, said third adjust time being larger than said second adjust time and substantially proportional to an interval or said detected pulse signal.

22. The disk drive apparatus in accordance with claim 14, further comprising

commanding means for producing said command signal which responds with an output pulse signal of said voltage detecting means.

23. A disk drive apparatus comprising;

a head for at least reproducing a signal from a disk or recording a signal on a disk;

processing means for at least processing an output signal from said head and outputting a reproducing information signal, or processing a recording information signal and outputting a signal into said head;

a rotor which has a field part generating field fluxes, and directly drives said disk;

Q-phase windings, Q being an integer of 3 or more;

voltage supplying means which include two output terminals for supplying a DC voltage;

power supplying means having Q first power transistors and Q second power transistors for supplying a power to said Q-phase windings, each of said Q first power transistors forming a current path between one output terminal side of said voltage supplying means and one of said Q-phase windings, and each of said Q second power transistors forming a current path between the other output terminal side of said voltage supplying means and one of said Q-phase windings;

activation control means for controlling said O first power transistors and said Q second power transistors; and

switching operation means for causing at least one power transistor among said Q first power transistors and said Q second power transistors to perform high-frequency switching corresponding to a command signal;

and that

said activation control means determines active periods of said Q first power transistors and said Q second power transistors, each of said active periods being larger than the period of 360/Q electrical degrees, and

said switching operation means includes;

current detecting means for producing a current detected signal which responds with or corresponds to a current from said voltage supplying means to said Q-phase windings, and

switching control means for producing a main switching pulse signal and an auxiliary switching pulse signal which respond with said current detected signal and said command signal, providing a time between an effective period of said main switching pulse signal and an effective period of said auxiliary switching pulse signal, causing at least one of said Q first power transistors to become ON in the effective period of said main switching pulse signal, causing at least one of said Q second power transistors to become ON in the effective period of said auxiliary switching pulse signal, and executing high-frequency switching operation of at least one second power transistor among said Q second power transistors responding with said auxiliary switching pulse signal when two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while at least another second power transistor among said Q second power transistors executes ON operation.

24. The disk drive apparatus in accordance with claim 23, wherein

said switching control means executes high-frequency switching operation of two second power transistors among said Q second power transistors simultaneously responding with said auxiliary switching pulse signal when said two first power transistors among said Q first power transistors simultaneously execute high-frequency switching operation responding with said main switching pulse signal while said at least another second power transistor among said Q second power transistors executes ON operation.

25. The disk drive apparatus in accordance with claim 23, wherein

said activation control means produces Q-phase first activation signals, each of which has an active period larger than 360/Q degree and responds with said main switching pulse signal, so as to control said Q first power transistors, and produces Q-phase second activation control signals, each of which has an active period larger than 360/Q degree and responds with said auxiliary switching pulse signal, so as to control said Q second power transistors.

26. The disk drive apparatus in accordance with claim 23, wherein

said voltage detecting means stops detecting of said detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of said at least one power transistor and a second stop period including another changing timing from ON to OFF of said at least one power transistor, and executes detecting of said detected pulse signal during at least ON period of said at least one power transistor excluding said at least one of said first stop period and said second stop period, thereby producing said detected pulse signal which responds with terminal voltages of said Q-phase windings.