Semiconductor integrated circuit device

• US 6,639,455 B2
• Filed: 01/24/2003
• Issued: 10/28/2003
• Est. Priority Date: 06/16/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Mizuno, Hiroyuki
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US10/350,084
• Publication Number:
  US 20030109966A1
• Time in Patent Office: 277 Days
• Field of Search: 327/530, 327/534, 327/535, 327/544, 327/545, 327/546
• US Class Current: 327/544
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Claims

1. A semiconductor device having a predetermined maximum power consumption, comprising:

a control circuit; and

a plurality of first circuits,

wherein each of the plurality of first circuits has a plurality of states, a degree of suppression of power consumption being different between each of the plurality of states, and

further wherein the control circuit determines a schedule of the states of each of the plurality of first circuits so that a total power consumption of the semiconductor device does not exceed said predetermined maximum power consumption.

2. The semiconductor device according to claim 1, wherein said plurality of states for each of said plurality of first circuits include an active state, a standby state and a sleep state.

3. The semiconductor device according to claim 1, wherein said predetermined power consumption is stored in a non-volatile memory.

4. The semiconductor device according to claim 1, further comprising:

a second circuit which issues to the control circuit a request to operate at least one of the plurality of first circuits,

wherein the control circuit reorders the schedule of the states in response to said request.

5. The semiconductor device according to claim 4, wherein said control circuit issues an acknowledgement to the second circuit corresponding to said request when the control circuit determines that said request to operate at least one of the plurality of first circuits is allowed.

6. The semiconductor device according to claim 5, wherein, when the control circuit issues the acknowledgement to the second circuit, the control circuit controls the requested first circuit to put the requested first circuit in one of the plurality of states in which the requested first circuit can operate.

7. The semiconductor device according to claim 1, wherein, in one of the plurality of states, the first circuit is not supplied with a clock signal.

8. The semiconductor device according to claim 1, wherein, in one of the plurality of states, the first circuit is not supplied with a supply voltage.

9. The semiconductor device according to claim 1, wherein the predetermined maximum power consumption is determined based upon the required performance of the semiconductor device.

10. The semiconductor device according to claim 1, wherein said control circuit and said plurality of first circuits are housed in a single package.

11. The semiconductor device according to claim 1, wherein said control circuit and said plurality of first circuits are integrated on a single semiconductor substrate.

12. A power control method for controlling a power consumption of a semiconductor device, comprising the steps of:

providing the semiconductor device including a control circuit and a plurality of first circuits, each of the plurality of first circuits having a plurality of states, a degree of suppression of power consumption being different between each of the plurality of states; and

arranging a schedule of the states of each of the plurality of first circuits by the control circuit so that a total power consumption of the semiconductor device does not exceed a predetermined maximum power consumption.

13. The power control method according to claim 12, wherein said plurality of states for each of said plurality of first circuits include an active state, a standby state and a sleep state.

14. The power control method according to claim 12, wherein the semiconductor device includes a second circuit.

15. The power control method according to claim 14, further comprising the steps of:

issuing a request to operate at least one of the plurality of first circuits, said request being issued by the second circuit to the control circuit;

rearranging, by the control circuit, the schedule of the states according to said request; and

issuing an acknowledgement corresponding to said request when the control circuit determines that said request to operate at least one of the plurality of first circuits is allowed, said acknowledgement being sent by the control circuit to the second circuit.

16. The power control method according to claim 15, further comprising the steps of:

controlling the requested first circuit to put the requested first circuit in one of the plurality of states in which the requested first circuit can operate, said control circuit controlling the requested first circuit when the control circuit issues the acknowledgement to the second circuit.

17. The power control method according to claim 12, further comprising the step of:

stopping the supply to the first circuit of a clock signal when the first circuit is in a state of the plurality of states in which the power consumption of the first circuit is suppressed.

18. The power control method according to claim 12, further comprising the step of:

stopping the supply to the first circuit of a supply voltage when the first circuit is in a state of the plurality of states in which the power consumption of the first circuit is suppressed.